PZ5064

The PZ5064 is designed as CPLD (complex programmable logic device) which is a member of fast zero power family of CPLDs from philips semiconductors.

PZ5064 has many features. The first one is industry's first totalCMOS PLD - both CMOS design and process technologies. The next one is fast zero power design technique provides ultra-low power and very high speed. The next oneis high speed pin-to-pin delays of 7.5ns. The next one is ultra-low static power of less than 100uA. The next one is dynamic power that is 70% lower at 50MHz than competing devices. The next one is 100% routable with 100% utilization while all pins and all macrocells are fixed. The next one is deterministic timing model that is extremely simple to use. The next one is up to 4 clocks with programmable polarity at every macrocell. And so on. That are all the main features.

Some absolute maximum ratings of PZ5064 have been concluded into several points as follow. The first one is about its supply voltage which would be min -0.5V and max 7.0V. The next one is about its input voltage which would be min -1.2V and max Vdd+0.5V. The next one is about its output voltage which would be min -0.5V and max Vdd+0.5V. The next one is about its input current which would be min -30mA and max 30mA. The next one is about its output current which would be min -100mA and max 100mA. The next one is about its maximum junction temperature range which would be min -40°C to 150°C. The next one is about its storage temperature range which would be from -65 to 150°C. It should be noted that stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification is not implied. And so on. For more information please contact us.