PZ47807-2747-01, PZ47807-2748-01, PZ47807-2748-01 (PB)

The PZ47807-2748-01 is a digitally configurable, multi- stage counter circuit in a single 8 pin package. When connected to a 60Hz source, four time periods from one hour to one week are possible, as shown in Table 1 below.Although the circuit has been optimized for a 60Hz input frequency, it is capable of being operated over a very wide range of frequencies. Of particular interest is the ability to interface directly to very low frequencies with varying waveforms due to the use of a Schmitt trigger input circuit.The PZ47807-2748-01 system controller includes a reset controller capable of managing the power-on sequence of the microcontroller and the complete system. Correct device operation can be monitored by a built-in brownout detector and a watchdog running off an integrated RC oscillator.I/O performance is increased to 622 Mb/s using Source Synchronous data transmission architectures and synchro- nous system performance up to 240 MHz using sin- gled-ended SelectI/O technology. Additional I/O standards are supported, notably LVPECL, LVDS, and BLVDS, which use two pins per signal. Almost all signal pins can be used for these new standards.

The PZ47807-2748-01 are high-speed, low-power, FIFO memories with clocked read and write interfaces. All devices are nine bits wide. The PZ47807-2748-01/PZ47807-2748-01 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, video and communications buffering. This method fails if a user applies RESET during the FPGA configuration process. The FPGA aborts the configuration and then restarts a new configuration, as intended, but the PROM does not reset its address counter, since it never saw a High level on its OE input. The new configuration, therefore, reads the remaining data in the PROM and inter- prets it as preamble, length count etc. Since the FPGA is the master, it issues the necessary number of CCLK pulses, up to 16 million (224) and DONE goes High.

For the adjustment of the resonance frequency the capacitance of the probe and the input capacitance of the IC are to be taken into account. The alignment should be done in the final environment. The bandwidth is so low that metal parts close to the antenna influence the resonance frequency. The adjustment can be done by pushing the coil along the bar antenna.