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NLSF308MNR2G, NLSF3T125, NLSF3T125MN

Table of contents:
Info of NLSF308MNR2G
Info of NLSF3T125
Info of NLSF3T125MN

NLSF308MNR2G, NLSF3T125, NLSF3T125MN Selling Leads, Datasheet

MFG:ON Semiconductor Category:Integrated Circuits (ICs) Package Cooled:2008 D/C:QFN-16

NLSF308MNR2G, NLSF3T125, NLSF3T125MN Picture

NLSF308MNR2G, NLSF3T125, NLSF3T125MN Datasheet download

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Part Number: NLSF308MNR2G

Category: Integrated Circuits (ICs)

MFG: ON Semiconductor

Package Cooled: 2008

D/C: QFN-16

Description: IC GATE AND QUAD 2INPUT 16-QFN

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NLSF308MNR2G Parameters

Technical/Catalog Information	NLSF308MNR2G
Vendor	ON Semiconductor
Category	Integrated Circuits (ICs)
Number of Circuits	4 - Quad
Package / Case	16-QFN
Logic Type	AND Gate
Packaging	Tape & Reel (TR)
Mounting Type	Surface Mount
Number of Inputs	2
Current - Output High, Low	8mA, 8mA
Supply Voltage	2 V ~ 5.5 V
Operating Temperature	-40°C ~ 85°C
Voltage - Supply	2 V ~ 5.5 V
Drawing Number	*
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	NLSF308MNR2G NLSF308MNR2G

NLSF3T125 General Description

The NLSF3T125 is a high speed CMOS quad bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.

The NLSF3T125 requires the 3?state control input (OE) to be set High to place the output into the high impedance state.

The T125 inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3 V to 5.0 V, because it has full 5.0 V CMOS level output swings.

The NLSF3T125 input structures provide protection when voltages between 0 V and 5.5 V are applied, regardless of the supply voltage. The output structures also provide protection when VCC = 0 V. These input and output structures help prevent device destruction caused by supply voltage input/output voltage mismatch, battery backup, hot insertion, etc.

The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems.

NLSF3T125 Maximum Ratings

Symbol	Parameter	Value	Unit
V_CC	DC Supply Voltage	-0.5 to +70	V
V_in	DC Input Voltage	-0.5 to +70	V
V_out	DC Output Voltage	-0.5 to +70 -0.5 to V_CC +0.5	V
I_Ik	Input Diode Current	-20	mA
I_OK	Output Diode Current (VOUT VCC	±20	mA
I_out	DC Output Current,per Pin	±25	mA
I_CC	DC Supply Current,VCC and GND Pins	±75	mA
P_D	Power Dissipation in Still Air,QFN Packages	500	mW
T_stg	Storage Temperature	-65 to +150

Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected. Functional operation should be restricted to the Recommended Operating Conditions.

NLSF3T125 Features

`High Speed: t_PD = 3.8 ns (Typ) at V_CC = 5.0 V
`Low Power Dissipation: I_CC = 4.0 A (Max) at T_A = 25
`TTL-Compatible Inputs: V_IL = 0.8 V; V_IH = 2.0 V
`Power Down Protection Provided on Inputs
`Balanced Propagation Delays
`Designed for 2.0 V to 5.5 V Operating Range
`Low Noise: V_OLP = 0.8 V (Max)
`Pin and Function Compatible with Other Standard Logic Families
`Latchup Performance Exceeds 300 mA
`ESD Performance:Human Body Model; > 2000 V,
Machine Model; > 200 V
`Chip Complexity: 72 FETs or 18 Equivalent Gates

NLSF3T125 Connection Diagram

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