MX29F002, MX29F002-12, MX29F002BPC-12 Selling Leads, Datasheet
MFG:MACRONIX Package Cooled:TSOP-32 D/C:04+
MX29F002, MX29F002-12, MX29F002BPC-12 Datasheet download
Part Number: MX29F002
MFG: MACRONIX
Package Cooled: TSOP-32
D/C: 04+
MX29F002, MX29F002-12, MX29F002BPC-12
- Table of contents:
Info of MX29F002
Info of MX29F002-12
Info of MX29F002BPC-12
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About MX29F002
PDF/DataSheet Download
Datasheet: MX29F002
File Size: 200998 KB
Manufacturer: MCNIX [Macronix International]
Download : Click here to Download
About MX205Q
PDF/DataSheet Download
Datasheet: MX205Q
File Size: 252911 KB
Manufacturer: ETC [ETC]
Download : Click here to Download
About MX29F002BPC-12
PDF/DataSheet Download
Datasheet: MX29F002BPC-12
File Size: 933679 KB
Manufacturer: MCNIX [Macronix International]
Download : Click here to Download
MX29F002 General Description
The MX29F002T/B is a 2-mega bit Flash memory organ-ized as 256K bytes of 8 bits only. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29F002T/B is packaged in 32-pin PDIP,PLCC and 32-pin TSOP(I). It is designed to be reprogrammed and erased in-system or in-standard EPROM programmers.
The standard MX29F002T/B offers access time as fast as 55ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX29F002T/B has separate chip enable ( CE) and output enable ( OE) controls.
MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29F002T/B uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility.
MXIC's Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The MX29F002T/B uses a 5.0V ± 10% VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms.
The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.
The standard MX29F002T/B offers access time as fast as 55ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX29F002T/B has separate chip enable ( CE) and output enable ( OE) controls.
MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29F002T/B uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility.
MXIC's Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The MX29F002T/B uses a 5.0V ± 10% VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms.
The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.
MX29F002 Maximum Ratings
| RATING |
VALUE |
|---|---|
| Ambient Operating Temperature |
0oC to 70oC |
| Storage Temperature |
-65oC to 125oC |
| Applied Input Voltage |
-0.5V to 7.0V |
| Applied Output Voltage |
-0.5V to 7.0V |
| VCC to Ground Potential |
-0.5V to 7.0V |
| A9 |
-0.5V to 13.5V |
MX29F002 Features
• 262,144x 8 only
• Fast access time: 55/70/90/120ns
• Low power consumption
- 30mA maximum active current(5MHz)
- 1uA typical standby current
• Programming and erasing voltage 5V ± 10%
• Command register architecture
- Byte Programming (7us typical)
- Sector Erase (16K-Byte x1, 8K-Byte x 2, 32K-Byte x1, and 64K-Byte x 3)
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors or the whole chip with Erase Suspend capability.
- Automatically programs and verifies data at specified address
• Erase Suspend/Erase Resume
- Data polling & Toggle bit for detection of program and erase cycle completion.
• Sector protection
- Hardware method to disable any combination of sectors from program or erase operations
- Sector protect/unprotect for 5V only system or 5V/12V system
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1 to VCC+1V
• Boot Code Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
• Hardware RESET pin(only for 29F002T/B)
- Resets internal state machine to read mode
• Low VCC write inhibit is equal to or less than 3.2V
• Package type:
- 32-pin PDIP
- 32-pin PLCC
- 32-pin TSOP (Type 1)
• 20 years data retention
- Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation.
• Status Reply
• Fast access time: 55/70/90/120ns
• Low power consumption
- 30mA maximum active current(5MHz)
- 1uA typical standby current
• Programming and erasing voltage 5V ± 10%
• Command register architecture
- Byte Programming (7us typical)
- Sector Erase (16K-Byte x1, 8K-Byte x 2, 32K-Byte x1, and 64K-Byte x 3)
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors or the whole chip with Erase Suspend capability.
- Automatically programs and verifies data at specified address
• Erase Suspend/Erase Resume
- Data polling & Toggle bit for detection of program and erase cycle completion.
• Sector protection
- Hardware method to disable any combination of sectors from program or erase operations
- Sector protect/unprotect for 5V only system or 5V/12V system
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1 to VCC+1V
• Boot Code Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
• Hardware RESET pin(only for 29F002T/B)
- Resets internal state machine to read mode
• Low VCC write inhibit is equal to or less than 3.2V
• Package type:
- 32-pin PDIP
- 32-pin PLCC
- 32-pin TSOP (Type 1)
• 20 years data retention
- Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation.
• Status Reply
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