ML53812-2, ML53812-2TC, ML541 Selling Leads, Datasheet
MFG:OKI Package Cooled:2006+ D/C:2
ML53812-2, ML53812-2TC, ML541 Datasheet download
Part Number: ML53812-2
MFG: OKI
Package Cooled: 2006+
D/C: 2
MFG:OKI Package Cooled:2006+ D/C:2
ML53812-2, ML53812-2TC, ML541 Datasheet download
MFG: OKI
Package Cooled: 2006+
D/C: 2
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Datasheet: ML53812-2
File Size: 684339 KB
Manufacturer: OKI [OKI electronic componets]
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PDF/DataSheet Download
Datasheet: ML53001
File Size: 124720 KB
Manufacturer: OKI
Download : Click here to Download
PDF/DataSheet Download
Datasheet: ML53001
File Size: 124720 KB
Manufacturer: OKI
Download : Click here to Download
The ML53812-2 is a complete CT Bus system interface and time slot interchange device that provides a cost-effective connection between a computer board's telephony interfaces or signal processing resources and the CT Bus. The ML53812-2 is an evolution of existing time-slot interchange ICs which offers seamless interoperability with SCbus devices.
A key element in computer telephony (CT) equipment is the auxiliary telecom bus. Most manufacturers of high-capacity CT equipment have used one or more types of telecom buses to transport and switch low-latency communications traffic between boards within the computer, bypassing the computer's main I/O and memory buses. To simplify the integration of devices that incorporate a telecom bus, the Enterprise Computer Telephony Forum (ECTF) developed a standard bus (H.100/H.110 CT Bus™) that provides compatibility modes with the most prevalent telecom buses today (SCbus™ and MVIP-90™), as well as the capacity and feature set needed to support the next generation of high capacity CT servers.
The new CT Bus is embraced by Dialogic under the Signal Computing System Architecture™ (SCSA™) umbrella of open standards for building interoperable CT systems.
The ML53812-2 runs in both 4 MHz and 8 MHz SCbus modes and supports the switching features needed to integrate CT Bus devices with 4 MHz SCbus, 8 MHz SCbus, and 2 MHz MVIP-90 devices. Because the H.100/H.110 CT Bus uses an identical switching model and clock speeds to that used for the SCbus, developers have unparalleled flexibility in integrating these two types of devices, or in transitioning from one type to the other.
The ML53812-2 takes full advantage of the mandatory and optional features defined in the ECTF H.100 and H.110 interoperability specifications. It is a non-blocking 512 x 4096 time slot switch, interfacing up to 512 ports on its parent device to any of the 4096 time slots on the new CT Bus. The high number of local time slots available makes it easier to design high-density CT hardware, supporting as many as eight network interfaces or 256 voice processing ports per chip.
This powerful chip is offered in an ultra slim profile (176-pin LQFP package, with a 24 mm x 24 mm x 1.4 mm body size) that makes it possible to mount the chip on either side of the board. The chip is fully software programmable, and can be controlled by a variety of microprocessors, including Intel and Motorola in both multiplexed and nonmultiplexed modes.
Parameter |
Symbol |
Test Conditions |
Min |
Max |
Unit |
Storage Temperature |
TS |
-65 |
150 |
||
Power Supply Voltage |
VPS |
-0.3 |
4.6 |
V | |
Input Voltage |
VI |
-0.3 |
6 |
V |
• High functionality, low cost implementation of the ECTF H.100/H.110 interoperability specifications.
• Simple to connect PCI and cPCI™ board-level circuitry to the universally accepted CT Bus™.
• Ultra slim profiling (176-pin LQFP package).
• Up to 512 programmable connections (256 transmit and 256 receive) to any of the 4096 time slots on the H.100/H.110 CT Bus.
• 8-channel stream-to-stream switching for data stream connections at variable rates.
• Implementation of all compatibility signals for complete interoperability with existing 4 MHz SCbus™, 8 MHz SCbus, 2 MHz MVIP-90™ devices, and H-MVIP™.
• Provides reliable clock synchronization for network-grade connection to digital network interfaces.
• Supports all H.100/H.110 CT Bus clock fallback features.
• Choice of constant or minimum switching delay on a per time slot basis.
• 3.3 V I/O with 5 V tolerant input.
• Supports multiplexed and nonmultiplexed address/data bus modes for both Intel and Motorola microprocessors.
• Supports CT Bus optional message channel interface, for both H.100 (PCI) and H.110 (cPCI) applications.
• Supports a variety of framing formats via a configurable local bus.
• Efficient microprocessor interface access to Local and CT Bus data streams through direct parallel access to/from transmit and receive switch.