M2S196493A0, M2S56D20ATP, M2S56D20ATP-75 Selling Leads, Datasheet
MFG:MOT Package Cooled:TSOP D/C:New
M2S196493A0, M2S56D20ATP, M2S56D20ATP-75 Datasheet download
Part Number: M2S196493A0
MFG: MOT
Package Cooled: TSOP
D/C: New
M2S196493A0, M2S56D20ATP, M2S56D20ATP-75
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Info of M2S196493A0
Info of M2S56D20ATP
Info of M2S56D20ATP-75
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About M2S12D20TP
PDF/DataSheet Download
Datasheet: M2S12D20TP
File Size: 772135 KB
Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]
Download : Click here to Download
About M2S56D20ATP
PDF/DataSheet Download
Datasheet: M2S56D20ATP
File Size: 786977 KB
Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]
Download : Click here to Download
About M2S56D20ATP-75
PDF/DataSheet Download
Datasheet: M2S56D20ATP-75
File Size: 786977 KB
Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]
Download : Click here to Download
M2S56D20ATP General Description
M2S56D20ATP is a 4-bank x 16,777,216-word x 4-bit, M2S56D30ATP is a 4-bank x 8,388,608-word x 8-bit, M2S56D40ATP is a 4-bank x 4,194,304-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output data and data strobe are referenced on both edges of CLK. The M2S56D20/30/40ATP achieves very high speed data rate up to 133MHz, and are suitable for main memory in computer systems.
M2S56D20ATP Maximum Ratings
|
Symbol |
Parameter |
Conditions |
Ratings |
Unit |
| Vdd | Supply Voltage |
with respect to Vss |
-0.5 ~ 3.7 |
V |
| VddQ | Supply Voltage for Output |
with respect to VssQ |
-0.5 ~ 3.7 |
V |
| VI | Input Voltage |
with respect to Vss |
-0.5 ~ Vdd+0.5 |
V |
| VO | Output Voltage |
with respect to VssQ |
-0.5~ VddQ+0.5 |
V |
| IO | Output Current |
50 |
mA | |
| Pd | Power Dissipation |
Ta = 25 |
1000 |
mW |
| Topr | Operating Temperature |
0 ~ 70 |
||
| Tstg | Storage Temperature |
-65 ~ 150 |
M2S56D20ATP Features
·Vdd=Vddq=2.5V+0.2V
·Double data rate architecture; two data transfers per clock cycle
·Bidirectional, data strobe (DQS) is transmitted/received with data
·Differential clock inputs (CLK and /CLK)
·DLL aligns DQ and DQS transitions with CLK transitions edges of DQS
·Commands entered on each positive CLK edge;
·data and data mask referenced to both edges of DQS
·4 bank operation controlled by BA0, BA1 (Bank Address)
·/CAS latency- 2.0/2.5 (programmable)
·Burst length- 2/4/8 (programmable)
·Burst type- sequential / interleave (programmable)
·Auto precharge / All bank precharge controlled by A10
·8192 refresh cycles /64ms (4 banks concurrent refresh)
·Auto refresh and Self refresh
·Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)
·SSTL_2 Interface
·400-mil, 66-pin Thin Small Outline Package (TSOP II)
·JEDEC standard
·Double data rate architecture; two data transfers per clock cycle
·Bidirectional, data strobe (DQS) is transmitted/received with data
·Differential clock inputs (CLK and /CLK)
·DLL aligns DQ and DQS transitions with CLK transitions edges of DQS
·Commands entered on each positive CLK edge;
·data and data mask referenced to both edges of DQS
·4 bank operation controlled by BA0, BA1 (Bank Address)
·/CAS latency- 2.0/2.5 (programmable)
·Burst length- 2/4/8 (programmable)
·Burst type- sequential / interleave (programmable)
·Auto precharge / All bank precharge controlled by A10
·8192 refresh cycles /64ms (4 banks concurrent refresh)
·Auto refresh and Self refresh
·Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)
·SSTL_2 Interface
·400-mil, 66-pin Thin Small Outline Package (TSOP II)
·JEDEC standard
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