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IDTCSPT857PAI, IDTCSPU877, IDTCSPU877A

Table of contents:
Info of IDTCSPT857PAI
Info of IDTCSPU877
Info of IDTCSPU877A

IDTCSPT857PAI, IDTCSPU877, IDTCSPU877A Selling Leads, Datasheet

MFG:TSSOP48 Package Cooled:74 D/C:IDT

IDTCSPT857PAI, IDTCSPU877, IDTCSPU877A Picture

IDTCSPT857PAI, IDTCSPU877, IDTCSPU877A Datasheet download

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Part Number: IDTCSPT857PAI

MFG: TSSOP48

Package Cooled: 74

D/C: IDT

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IDTCSPU877 General Description

The CSPU877 is a PLL based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(CLK, CLK ) to 10 differential output pairs (Y [0:9], Y [0:9]) and one differential pair of feedback clock output (FBOUT, FBOUT). External feedback pins (FBIN, FBIN) for synchronization of the outputs to the input reference is provided. OE, OS, and AVDD control the power-down and test mode logic. When AVDD is grounded, the PLL is turned off and bypassed for test mode purposes. When the differential clock inputs (CLK, CLK) are both at logic low, this device will enter a low power-down mode. In this mode, the receivers are disabled, the PLL is turned off, and the output clock drivers are disabled, resulting in a current consumption device of less than 500µA.

The CSPU877 requires no external components and has been optimised for very low phase error, skew, and jitter, while maintaining frequency and duty cycle over the operating voltage and temperature range.

The CSPU877, designed for use in both module assemblies and system motherboard based solutions, provides an optimum high-performance clock source. The CSPU877 is available in Commercial Temperature Range (0°C to +70°C). See Ordering Information for details.

IDTCSPU877 Maximum Ratings

Rating	Symbol	Max	unit
Supply Voltage Range	V _CC1, V_CC2	0.5 to +4.6	V
Input Voltage Range	V_I⁽²⁾	0.5 to +5.5	V
Voltage range applied to any output in the high or low state	V_O⁽²⁾	0.5 to VDD + 0.5	V
Input clamp current	I_IK (VI < 0)	50	mA
Terminal Voltage with Respect to GND (inputs VIH 2.5, VIL 2.5)	I_OK (V_O < 0 or V_O> V_DD)	-50	mA
Continuous Output Current	I_RES	±100	mA
Continuous Current	V_DDor G_ND	100	mA
Storage Temperature Range	T_STG	65 to +150	°C

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
3. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to 2.5V max.

IDTCSPU877 Features

• 1 to 10 differential clock distribution
• Optimized for clock distribution in DDR2 (Double Data Rate) SDRAM applications
• Operating frequency: 125MHz to 400MHz
• Very low skew: 40ps
• Very low jitter: 40ps
• 1.8V AVDD and 1.8V VDDQ
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock

IDTCSPU877 Typical Application

• Meets or exceeds JEDEC standard 82.8 for registered DDR2 clock driver
• Along with SSTU32864/A, DDR2 register, provides complete solution for DDR2 DIMMs

IDTCSPU877 Connection Diagram

IDTCSPU877A General Description

The CSPU877A is a PLL based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(CLK, CLK</a> ) to 10 differential output pairs (Y [0:9]</a>,Y [0:9]) and one differential pair of feedback clock output (FBOUT, FBOUT</a>). External feedback pins (FBIN, FBIN</a>) for synchronization of the outputs to the input reference is provided. OE, OS, and AVDD control the power-down and test mode logic. When AVDD is grounded, the PLL is turned off and bypassed for test mode purposes. When the differential clock inputs (CLK, CLK</a>) are both at logic low, this device will enter a low power-down mode.In this mode, the receivers are disabled, the PLL is turned off, and the output clock drivers are disabled, resulting in a current consumption device of less than 500µA.

The CSPU877A requires no external components and has been optimised for very low phase error, skew, and jitter, while maintaining frequency and duty cycle over the operating voltage and temperature range. The CSPU877A, designed for use in both module assemblies and system motherboard based
solutions, provides an optimum high-performance clock source.

The CSPU877A is available in Commercial Temperature Range (0°C to+70°C). See Ordering Information for details.

IDTCSPU877A Maximum Ratings

Symbol	Rating	Max	Unit
V_DDQ, A_VDD	Supply Voltage Range	0.5 to +2.5	V
VI⁽³⁾	Input Voltage Range	0.5 to V_DDQ+0.5	V
VO⁽³⁾	Voltage range applied to any output in the high or low state	0.5 to V_DDQ+0.5	V
IIK (VI <0)	Input Clamp Current	50	mA
IOK (VO <0 or VO > V_DDQ)	Output Clamp Current	±50	mA
IO (VO =0 to V_DDQ)	Continuous Output Current	±50	mA
V_DDQ or GND	Continuous Current	±100	mA
TSTG	Storage Temperature Range	65 to +150	°C

IDTCSPU877A Features

•1 to 10 differential clock distribution
•Optimized for clock distribution in DDR2 (Double Data Rate) SDRAM applications
•Operating frequency: 125MHz to 270MHz
•Very low skew: 40ps
•Very low jitter: 40ps
•1.8V AV_DD and 1.8V V_DDQ
•CMOS control signal input
•Test mode enables buffers while disabling PLL
•Low current power-down mode
•Tolerant of Spread Spectrum input clock
•Available in 52-Ball VFBGA and 40-pin MLF packages

IDTCSPU877A Typical Application

•Meets or exceeds JEDEC standard 82.8 for registered DDR2 clock driver
•Along with SSTU32864/65/66, DDR2 register, provides complete solution for DDR2 DIMMs

IDTCSPU877A Connection Diagram

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