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IDT RC5000

Features: • Dual issue super-scalar execution core, executing at high-frequency- 250 MHz frequency- Dual issue floating-point ALU operations with other instruction classes- Traditional 5-stage pipeline, minimizes load and branch latencies- Single cycle repeat rate for most floating point ALU...

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SeekIC No. : 004371633 Detail

IDT RC5000: Features: • Dual issue super-scalar execution core, executing at high-frequency- 250 MHz frequency- Dual issue floating-point ALU operations with other instruction classes- Traditional 5-stage...

IDT RC5000 Data Sheet

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Part Number:
IDT RC5000
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Dual issue super-scalar execution core, executing at high-frequency
- 250 MHz frequency
- Dual issue floating-point ALU operations with other instruction classes
- Traditional 5-stage pipeline, minimizes load and branch latencies
- Single cycle repeat rate for most floating point ALU operations
• High level of performance for a variety of applications
- High-performance 64-bit integer unit achieves 330 dhrystone MIPS (dhrystone 2.1)
- Ultra high-performance floating-point accelerator, directly implementing single- and double-precision operations achieves 500mflops
- Extremely large on-chip primary caches
- On-chip secondary cache controller
• Large, efficient on-chip caches
- 32KB Instruction Cache, 32KB Data Cache
- 2-set associative in each cache
- Virtually indexed and physically tagged to minimize cache flushes
- Write-back and write-through selectable on a per page basis
- Critical word first cache miss processing
- Supports back-to-back loads and stores in any combination at full pipeline rate
• High-performance memory system
- Large primary caches integrated on-chip
- Secondary cache control interface on-chip
- High-frequency 64-bit bus interface runs up to 100MHz
- Aggregate bandwidth of on-chip caches, system interface of 5GB/s
- High-performance write protocols for graphics and data communications
• MIPS-IV 64-bit ISA for improved computation
- Compound floating-point operations for 3D graphics and floating-point DSP
- Conditional move operations
• Compatible with a variety of operating systems
- Windows™ CE
- Numerous MIPS-compatible real-time operating systems
• Uses input system clock, with processor pipeline clock multiplied by a factor of 2-8
• Large on-chip TLB
• Active power management, including use of WAIT operation


Specifications

Symbol
Rating
RC5000
3.3V±5%
Unit
Commercial

VTERM
Terminal Voltage with respect to GND
0.5(2) to +4.6
V
TC
Operating Temperature (case)
0 to +85
°C
TBIAS
Case Temperature Under Bias
55 to +125
°C
TSTG
Storage Temperature
55 to +125
°C
IIN
DC Input Current
20(3)
mA
IOUT
DC Output Current
50(4)
mA

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VIN minimum = 2.0V for pulse width less than 15ns. VIN should not exceed VCC +0.5 Volts.
3. When VIN < 0V or VIN > VCC.
4. Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds.




Description

The IDT RC5000 serves many performance critical embedded applications, such as high-end internetworking systems, color printers, and graphics terminals.

The IDT RC5000 is optimized for high-performance applications, with special emphasis on system bandwidth and floating point operations, through integration of highperformance computational units and a high-performance memory hierarchy. For this class of application, the result is a relatively low-cost CPU capable of approximately 330 Dhrystone MIPS.
IDT's objectives in offering the IDT RC5000 include:
• Offering a high performance upgrade path to existing embedded customers in the internetworking, office automation and visualization markets.
• Providing a significant improvement in the floatingpoint performance currently available in a moderately priced MIPS CPU.
• Providing improvements in the memory hierarchy of desktop systems by using large primary caches and integrating a secondary cache controller.
• Enabling improvements in performance through the use of the MIPS-IV ISA.




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