IDTCSPT855, IDTCSPT857, IDTCSPT857A Selling Leads, Datasheet
MFG:N/A Package Cooled:N/A D/C:09+
IDTCSPT855, IDTCSPT857, IDTCSPT857A Datasheet download
Part Number: IDTCSPT855
MFG: N/A
Package Cooled: N/A
D/C: 09+
IDTCSPT855, IDTCSPT857, IDTCSPT857A
- Table of contents:
Info of IDTCSPT855
Info of IDTCSPT857
Info of IDTCSPT857A
Attentive hint
Want to post a buying lead? If you are not a member yet, please select the specific/related part number first and then fill the quantity and your contact details in the "Request for Quotation Form" on the left, and then click "Send RFQ".Your buying lead can then be posted, and the reliable suppliers will quote via our online message system or other channels soon.
Top Sellers:
TOP
About IDTCSPT855
PDF/DataSheet Download
Datasheet: IDTCSPT855
File Size: 80468 KB
Manufacturer: IDT
Download : Click here to Download
About IDTCSPT857/A
PDF/DataSheet Download
Datasheet: IDTCSPT857/A
File Size: 127264 KB
Manufacturer: IDT
Download : Click here to Download
About IDTCSPT857ABV
PDF/DataSheet Download
Datasheet: IDTCSPT857ABV
File Size: 127218 KB
Manufacturer: IDT [Integrated Device Technology]
Download : Click here to Download
IDTCSPT855 General Description
The CSPT855 is a high-performance, low-skew, low-jitter zero delay buffer that distributes one differential clock input pair(CLK, CLK ) to four differential output pairs (Y [0:3], Y [0:3]) and one differential pair of feedback clock outputs FBOUT, FBOUT). When PWRDWN is high, the outputs switch in phase and frequency with CLK. When PWRDWN is low, all outputs are disabled to a highimpedance state (3-state), and the PLL is shut down (low-power mode).
The device also enters this low-power mode when the input frequency falls below suggested detection frequency that is below 20MHz (typical 10MHz). An input frequency detection circuit detects the low-frequency condition, and after applying a >20MHz input signal, this detection circuit reactivates the PLL and enables the outputs. When AVDD is tied to GND, the PLL is turned off and bypassed for test purposes.
The CSPT855 is also able to track spread spectrum clocking reducted EMI. Since the CSPT855 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up.
IDTCSPT855 Maximum Ratings
|
Rating |
Symbol |
Max |
unit |
|
Supply Voltage Range |
V CC1, VCC2 |
0.5 to +4.6
|
V |
|
Input Voltage Range |
VI (2)
|
0.5 to +5.5 |
V |
|
Voltage range applied to any output in the high or low state |
VO(2) |
0.5 to VDD + 0.5
|
V |
|
Input clamp current |
IIK (VI < 0)
|
50 |
mA |
|
Terminal Voltage with Respect to GND (inputs VIH 2.5, VIL 2.5) |
IOK (VO < 0 or VO > VDD) |
-50
|
mA |
|
Continuous Output Current |
IRES |
±100 |
mA |
|
Continuous Current |
VDD or GND |
65 to +150 |
mA |
|
Junction Temperature |
TSTG |
+150 |
°C |
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed. This value is limited to 3.6V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
IDTCSPT855 Features
• PLL clock driver for DDR (Double Data Rate) synchronous DRAM applications
• Spread spectrum clock compatible
• Operating frequency: 60MHz to 180MHz
• Low jitter (cycle-to-cycle): ±50ps
• Distributes one differential clock input to four differential clock outputs
• Enters low power mode and 3-state outputs when input CLK signal is less than 20MHz or PWRDWN is low
• Operates from dual 2.5V supplies
• Consumes <200µA quiescent current
• External feedback pins (FBIN, FBIN) are used to synchronize outputs to input clocks
• Available in TSSOP package
• Spread spectrum clock compatible
• Operating frequency: 60MHz to 180MHz
• Low jitter (cycle-to-cycle): ±50ps
• Distributes one differential clock input to four differential clock outputs
• Enters low power mode and 3-state outputs when input CLK signal is less than 20MHz or PWRDWN is low
• Operates from dual 2.5V supplies
• Consumes <200µA quiescent current
• External feedback pins (FBIN, FBIN) are used to synchronize outputs to input clocks
• Available in TSSOP package
IDTCSPT855 Connection Diagram
IDTCSPT857 General Description
The CSPT857 is a PLL based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(CLK,CLK ) to 10 differential output pairs (Y [0:9], Y [0:9]) and one differential pair of feedback clock output (FBOUT, FBOUT).
External feedback pins (FBIN, FBIN) for synchronization of the outputs to the input reference is provided. A CMOS Enable/Disable pin is available for low power disable. When the output frequency falls below approximately 20MHz, the device will enter power down mode. In this mode, the receivers are disabled, the PLL is turned off, and the output clock drivers are tristated, resulting in a current consumption device of less than 200µA.
The CSPT857 requires no external components and has been optimised for very low I/O phase error, skew, and jitter, while maintaining frequency and duty cycle over the operating voltage and temperature range.
The CSPT857, designed for use in both module assemblies and system motherboard based solutions, provides an optimum high-performance clock source. The CSPT857 is only available in Industrial Temperature Range (-40°C to +85°C), and CSPT857A is only available in Commercial Temperature Range (0°C to +70°C). See Ordering Information for details.
IDTCSPT857 Maximum Ratings
|
Rating |
Symbol |
Max |
unit |
|
Supply Voltage Range |
V CC1, VCC2 |
0.5 to +4.6
|
V |
|
Input Voltage Range |
VI (2)
|
0.5 to +5.5 |
V |
|
Voltage range applied to any output in the high or low state |
VO(2) |
0.5 to VDDQ + 0.5
|
V |
|
Input clamp current |
IIK (VI < 0)
|
50 |
mA |
|
Terminal Voltage with Respect to GND (inputs VIH 2.5, VIL 2.5) |
IOK (VO < 0 or VO > VDD) |
-50
|
mA |
|
Continuous Output Current |
IRES |
±100 |
mA |
|
Continuous Current |
VDD or GND |
65 to +150 |
mA |
|
Junction Temperature |
TSTG |
+150 |
°C |
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
IDTCSPT857 Features
• Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications
• Operating frequency: 60MHz to 200MHz
• Standard speed: PC1600 (DDR200), PC2100 (DDR266)
• A speed: PC1600 (DDR200), PC2100 (DDR266), PC2700 (DDR333)
• 1 to 10 differential clock distribution
• Very low skew (<100ps)
• Very low jitter (<75ps)
• 2.5V AVDD and 2.5V VDDQ
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Available in 48-pin TSSOP and 56-pin VFBGA packages
SDRAM applications
• Operating frequency: 60MHz to 200MHz
• Standard speed: PC1600 (DDR200), PC2100 (DDR266)
• A speed: PC1600 (DDR200), PC2100 (DDR266), PC2700 (DDR333)
• 1 to 10 differential clock distribution
• Very low skew (<100ps)
• Very low jitter (<75ps)
• 2.5V AVDD and 2.5V VDDQ
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Available in 48-pin TSSOP and 56-pin VFBGA packages
IDTCSPT857 Connection Diagram
IDTCSPT857A General Description
The CSPT857 is a PLL based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(CLK,CLK ) to 10 differential output pairs (Y [0:9], Y [0:9]) and one differential pair of feedback clock output (FBOUT, FBOUT).
External feedback pins (FBIN, FBIN) for synchronization of the outputs to the input reference is provided. A CMOS Enable/Disable pin is available for low power disable. When the output frequency falls below approximately 20MHz, the device will enter power down mode. In this mode, the receivers are disabled, the PLL is turned off, and the output clock drivers are tristated, resulting in a current consumption device of less than 200µA.
The CSPT857 requires no external components and has been optimised for very low I/O phase error, skew, and jitter, while maintaining frequency and duty cycle over the operating voltage and temperature range.
The CSPT857, designed for use in both module assemblies and system motherboard based solutions, provides an optimum high-performance clock source. The CSPT857 is only available in Industrial Temperature Range (-40°C to +85°C), and CSPT857A is only available in Commercial Temperature Range (0°C to +70°C). See Ordering Information for details.
IDTCSPT857A Maximum Ratings
|
Rating |
Symbol |
Max |
unit |
|
Supply Voltage Range |
V CC1, VCC2 |
0.5 to +4.6
|
V |
|
Input Voltage Range |
VI (2)
|
0.5 to +5.5 |
V |
|
Voltage range applied to any output in the high or low state |
VO(2) |
0.5 to VDDQ + 0.5
|
V |
|
Input clamp current |
IIK (VI < 0)
|
50 |
mA |
|
Terminal Voltage with Respect to GND (inputs VIH 2.5, VIL 2.5) |
IOK (VO < 0 or VO > VDD) |
-50
|
mA |
|
Continuous Output Current |
IRES |
±100 |
mA |
|
Continuous Current |
VDD or GND |
65 to +150 |
mA |
|
Junction Temperature |
TSTG |
+150 |
°C |
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
IDTCSPT857A Features
• Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications
• Operating frequency: 60MHz to 200MHz
• Standard speed: PC1600 (DDR200), PC2100 (DDR266)
• A speed: PC1600 (DDR200), PC2100 (DDR266), PC2700 (DDR333)
• 1 to 10 differential clock distribution
• Very low skew (<100ps)
• Very low jitter (<75ps)
• 2.5V AVDD and 2.5V VDDQ
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Available in 48-pin TSSOP and 56-pin VFBGA packages
SDRAM applications
• Operating frequency: 60MHz to 200MHz
• Standard speed: PC1600 (DDR200), PC2100 (DDR266)
• A speed: PC1600 (DDR200), PC2100 (DDR266), PC2700 (DDR333)
• 1 to 10 differential clock distribution
• Very low skew (<100ps)
• Very low jitter (<75ps)
• 2.5V AVDD and 2.5V VDDQ
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Available in 48-pin TSSOP and 56-pin VFBGA packages
IDTCSPT857A Connection Diagram
MT58L64L18CT-10
Price: 4-6 USD
MT58L64L18CT-10 TQFP100
DL-7140-211M
Price: 5-6.5 USD
DL-7140-211M laser tube
74LVC74APG
Price: 4-5 USD
74LVC74APG - IC FLIP FLOP D-Type POS-EDG DUAL 14TSSOP
CY28346ZI-2
Price: 6.5-8 USD
CYPRESS - Clock Synthesizer with Differential CPU Outputs
PI5V330QEX
Price: 0.284-0.286 USD
PI5V330QEX Pericom Multiplexer Switch ICs
BSM300GA120DN2
Price: 1-2 USD
IGBT power module, Single switch, 1200 V, Collector-emitter voltage, 430A
SVA150XG04TB
Price: 1-2 USD
a-Si TFT-LCD, NEC, 228.096Hmm, 560V
PC354N1
Price: 0.124-0.2 USD
PC354N1T - Mini-flat Package, AC Input Type Photocoupler - Sharp Electrionic Components
RL1210JR-070R22L
Price: 0.177-0.178 USD
RL1210JR51-XX-BL - Thick Film Chip Resistor Low Ohmic - TAITRON Components Incorporated
STPS140A
Price: 0.053-0.055 USD
STPS140A - POWER SCHOTTKY RECTIFIER - STMicroelectronics
STA013
Price: 1.45-1.5 USD
STA013 - MPEG 2.5 LAYER III AUDIO DECODER - STMicroelectronics
SMBJ5347B
Price: 0.073-0.075 USD
SMBJ5347B - 5 Watt Surface Mount Silicon Zener Diodes - Micro Commercial Components
