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IDTCSP2510CPG8, IDTCSP2510D, IDTCSPF2510C

Table of contents:
Info of IDTCSP2510CPG8
Info of IDTCSP2510D
Info of IDTCSPF2510C

IDTCSP2510CPG8, IDTCSP2510D, IDTCSPF2510C Selling Leads, Datasheet

MFG:IDT, Integrated Device Technology Inc Category:Integrated Circuits (ICs) Package Cooled:N/A D/C:09+

IDTCSP2510CPG8, IDTCSP2510D, IDTCSPF2510C Picture

IDTCSP2510CPG8, IDTCSP2510D, IDTCSPF2510C Datasheet download

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Part Number: IDTCSP2510CPG8

Category: Integrated Circuits (ICs)

MFG: IDT, Integrated Device Technology Inc

Package Cooled: N/A

D/C: 09+

Description: IC PLL CLK DRIVER 3.3V 24-TSSOP

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IDTCSP2510CPG8 Parameters

Technical/Catalog Information	IDTCSP2510CPG8
Vendor	IDT, Integrated Device Technology Inc
Category	Integrated Circuits (ICs)
Type	PLL Clock Driver, Zero Delay Buffer
Voltage - Supply	3 V ~ 3.6 V
Number of Outputs	10
Input	Clock
Output	Clock
Frequency-Max	140MHz
Package / Case	24-TSSOP
Packaging	Tape & Reel (TR)
Operating Temperature	0°C ~ 70°C
Lead Free Status	Contains Lead
RoHS Status	RoHS Non-Compliant
Other Names	IDTCSP2510CPG8 IDTCSP2510CPG8

IDTCSP2510D General Description

The CSP2510D is a high performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs.

The CSP2510D operates at 3.3V. One bank of ten outputs provide low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. The outputs can be enabled or disabled via the control G input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CSP2510D does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CSP2510D requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for the test purposes by strapping AVDD to ground.

The CSP2510D is specified for operation from 0°C to +85°C. This device is also available (on special order) in Industrial temperature range (-40°C to +85°C). See ordering information for details.

IDTCSP2510D Maximum Ratings

Rating	Symbol	Max	unit
Supply Voltage Range	V _CC1, V_CC2	0.5 to +4.6	V
Input Voltage Range	V_I⁽²⁾	0.5 to +5.5	V
Voltage range applied to any output in the high or low state	V_O⁽²⁾	0.5 to VDD + 0.5	V
Input clamp current	I_IK (VI < 0)	50	mA
Terminal Voltage with Respect to GND (inputs VIH 2.5, VIL 2.5)	I_OK (V_O < 0 or V_O> V_DD)	-50	mA
Continuous Output Current	I_RES	±100	mA
Continuous Current	V_DDor G_ND	65 to +150	mA
Junction Temperature	T_STG	+150	°C

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150°C and a board trace length of 750 mils.

IDTCSP2510D Features

• Phase-Lock Loop Clock Distribution for Synchronous DRAM
Applications
• Distributes one clock input to one bank of ten outputs
• Output enable bank control
• External feedback (FBIN) pin is used to synchronize the
outputs to the clock input signal
• No external RC network required for PLL loop stability
• Operates at 3.3V VDD
• tpd Phase Error at 166MHz: < ±150ps
• Jitter (peak-to-peak) at 166MHz: < ±75ps @ 166MHz
• Spread Spectrum Compatible
• Operating frequency 50MHz to 175MHz
• Available in 24-Pin TSSOP package

IDTCSP2510D Typical Application

• SDRAM Modules
• PC Motherboards
• Workstations

IDTCSP2510D Connection Diagram

IDTCSPF2510C General Description

The IDTCSPF2510C is a high performance, low-skew, low-phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, infrequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs.

The CSPF2510C operates at 3.3V and provides integrated series-damping resistors that make it ideal for driving point-to-point loads, single or dual. One bank of ten outputs provide low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. The outputs can be enabled or disabled via the control G input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CSPF2510C does not require external RC networks.

The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CSPF2510C requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for the test purposes by strapping AVDD to ground.

The CSPF2510C is characterized for operation from 0°C to +85°C. This device is also available (on special order) in Industrial (-40°C to +85°C)

IDTCSPF2510C Maximum Ratings

Rating	Symbol	Max	unit
Supply Voltage Range	V _CC1, V_CC2	0.5 to +4.6	V
Input Voltage Range	V_I⁽²⁾	0.5 to +5.5	V
Voltage range applied to any output in the high or low state	V_O⁽²⁾	0.5 to VDD + 0.5	V
Input clamp current	I_IK (VI < 0)	50	mA
Terminal Voltage with Respect to GND (inputs VIH 2.5, VIL 2.5)	I_OK (V_O < 0 or V_O> V_DD)	-50	mA
Continuous Output Current	I_RES	±100	mA
Continuous Current	V_DDor G_ND	65 to +150	mA
Junction Temperature	T_STG	+150	°C

IDTCSPF2510C Features

• Phase-Lock Loop Clock Distribution for Synchronous DRAM
Applications
• Distributes one clock input to one bank of ten outputs
• Output enable bank control
• External feedback (FBIN) pin is used to synchronize the output
to the clock input signal
• On-chip series damping resistors with each driver
• No external RC network required for PLL loop stability
• Operates at 3.3V VDD
• tpd Phase Error at 133MHz: < ±150ps
• Jitter (cycle-cycle)(peak-to-peak) at 66MHz to 133MHz: | 70 | ps
• Spread Spectrum Compatible
• Operating frequency 25MHz to 140MHz
• Fully conforms to PC133 specifications
• Available in 24-Pin TSSOP package

IDTCSPF2510C Connection Diagram

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