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This 32-bit bus transceiver is built using advanced dual metal CMOS technology. This high-speed, low power transceiver is ideal for asynchronous communication between two busses (A and B). The Direction and Output Enable controls are designed to operate the device as either four independent 8-bit transceivers or one 32-bit transceiver. The direction control pins (DIR) control the direction of data flow. The output enable pins (OE) override the direction control and disable both ports. All inputs are designed with hysteresis for improved noise margin.
All pins can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system.
The LVCH32245A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance
The LVCH32245A has "bus-hold" which retains the inputs' last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.
IDT74LVCH32245A Maximum Ratings
Symbol
Description
Max
Unit
VTERM
Terminal Voltage with Respect to GND
0.5 to +6.5
V
TSTG
Storage Temperature
65 to +150
IOUT
DC Output Current
50 to +50
mA
IIK IOK
Continuous Clamp Current, VI < 0 or VO < 0
50
mA
ICC ISS
Continuous Current through each VCC or GND
±100
mA
IDT74LVCH32245A Features
• Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4µ W typ. static) • All inputs, outputs, and I/O are 5V tolerant • Supports hot insertion • Available in 96-ball LFBGA package
IDT74LVCH32245A Typical Application
• 5V and 3.3V mixed voltage systems • Data communication and telecommunication systems