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IDT74LVC11A, IDT74LVC125A, IDT74LVC126APG

Table of contents:
Info of IDT74LVC11A
Info of IDT74LVC125A
Info of IDT74LVC126APG

IDT74LVC11A, IDT74LVC125A, IDT74LVC126APG Selling Leads, Datasheet

MFG:N/A Package Cooled:N/A D/C:09+

IDT74LVC11A, IDT74LVC125A, IDT74LVC126APG Picture

IDT74LVC11A, IDT74LVC125A, IDT74LVC126APG Datasheet download

Five Points

Part Number: IDT74LVC11A

MFG: N/A

Package Cooled: N/A

D/C: 09+

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IDT74LVC11A General Description

The LVC11A triple 3-input AND gate is built using advanced dual metal CMOS technology. The LVC11A device provides the 3-input AND function.

Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V system environment.

The LVC11A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.

IDT74LVC11A Maximum Ratings

Symbol	Description	Max	Unit
V_TERM	Terminal Voltage with Respect to GND	0.5 to +6.5	V
T_STG	Storage Temperature	65 to +150	°C
I_OUT	DC Output Current	50 to +50	mA
I_IKI_OK	Continuous Clamp Current, V_I< 0 or V_O < 0	50	mA
I_CC I_SS	Continuous Current through each V_CC or GND	±100	mA

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

IDT74LVC11A Features

• 0.5 MICRON CMOS Technology
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
• V_CC = 3.3V ± 0.3V, Normal Range
• V_CC= 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4 W typ. static)
• Rail-to-Rail output swing for increased noise margin
• All inputs, outputs, and I/Os are 5V tolerant
• Supports hot insertion
• Available in SOIC, SSOP, and TSSOP packages

IDT74LVC11A Typical Application

• 3.3V high speed systems
• 3.3V and lower voltage computing systems

IDT74LVC11A Connection Diagram

IDT74LVC125A General Description

The LVC125A quadruple bus buffer gate is built using advanced dual metal CMOS technology. The LVC125A features independent line drivers with 3-state outputs. Each output is disabled when the associated outputenable (OE) input is high.

To ensure the high impedance state during power up or power down, OE should be tied to Vcc through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V system environment.

The LVC125A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.

IDT74LVC125A Maximum Ratings

Symbol	Description	Max	Unit
V_TERM	Terminal Voltage with Respect to GND	0.5 to +6.5	V
T_STG	Storage Temperature	65 to +150
I_OUT	DC Output Current	50 to +50	mA
I_IK I_OK	Continuous Clamp Current, V_I < 0 or V_O < 0	50	mA
I_CC I_SS	Continuous Current through each V_CC or GND	±100	mA

IDT74LVC125A Features

• 0.5 MICRON CMOS Technology
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• V_CC = 3.3V ± 0.3V, Normal Range
• V_CC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• All inputs, outputs, and I/Os are 5V tolerant
• Supports hot insertion
• Available in SOIC, SSOP, and TSSOP packages

IDT74LVC125A Typical Application

• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems

IDT74LVC125A Connection Diagram

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