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IDT74GJLP16612PA, IDT74GTLP16612, IDT74GTLP16621PA

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Info of IDT74GJLP16612PA
Info of IDT74GTLP16612
Info of IDT74GTLP16621PA

IDT74GJLP16612PA, IDT74GTLP16612, IDT74GTLP16621PA Selling Leads, Datasheet

MFG:IDT Package Cooled:09+ D/C:1000

IDT74GJLP16612PA, IDT74GTLP16612, IDT74GTLP16621PA Picture

IDT74GJLP16612PA, IDT74GTLP16612, IDT74GTLP16621PA Datasheet download

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Part Number: IDT74GJLP16612PA

MFG: IDT

Package Cooled: 09+

D/C: 1000

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IDT74GTLP16612 General Description

The GTLP16612 is an 18-bit universal bus transceiver. It provides signal level translation, from TTL to GTLP, for applications requiring a highspeed interface between cards operating at TTL logic levels and backplanes operating at GTLP logic levels. GTLP provides reduced output swing (<1V), reduced input threshold levels, and output edge-rate control to minimize signal setting times. The GTLP16612 is a derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD8-3 and incorporates internal edge-rate control, which is process, voltage, and temperature (PVT) compensated.

GTLP output low voltage is less than 0.5V. The output high is 1.5V, and the receiver threshold is 1V.

IDT74GTLP16612 Maximum Ratings

Symbol	Rating	Max.	Unit
VCC	Supply Voltage	0.5 to +7	V
VCCQ	Supply Voltage	0.5 to +7	V
VI	DC Input Voltage	0.5 to +7	V
VO	DC Output Voltage, 3-State	0.5 to +7	V
VO	DC Output Voltage, Active	0.5 to VCC + 0.5	V
IOL	DC Output Sink Current into A-port	64	mA
IOH	DC Output Source Current from A-port	64	mA
IOL	DC Output Sink Current into B-port(in the LOW state)	80	mA
IIK	DC Input Diode Current VI < 0V	50	mA
IOK	DC Output Diode Current VO < 0V	50	mA
IOK	DC Output Diode Current VO > VCC	+50	mA
TSTG	Storage Temperature	65 to +150	°C

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Unused inputs without Bus-Hold must be held HIGH or LOW.

IDT74GTLP16612 Features

• Bidirectional interface between GTLP and TTL logic levels
• Edge Rate Control Circuit reduces output noise
• VREF pin provides reference voltage for receiver threshold
• CMOS technology for low power dissipation
• Special PVT Compensation circuitry to provide consistent performance over variations of process, supply voltage,
and temperature
• 5V tolerant inputs and outputs on A-Port
• Bus-Hold to eliminate the need for external pull-up resistors for unused inputs to A-Port
• Power up/down high-impedance
• TTL-compatible Driver and Control inputs
• High Output source/sink ±32mA on A-Port pins
• Flow-through architecture optimizes system layout
• D-type latch and flip-flop architecture for data flow in clocked, transparent, or latched mode
• Open drain on GTLP to support wired OR connection
• Available in SSOP and TSSOP packages

IDT74GTLP16612 Connection Diagram

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