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IDT74FCT162344CTPA, IDT74FCT162344ET, IDT74FCT162371CTPA

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Info of IDT74FCT162344CTPA
Info of IDT74FCT162344ET
Info of IDT74FCT162371CTPA

IDT74FCT162344CTPA, IDT74FCT162344ET, IDT74FCT162371CTPA Selling Leads, Datasheet

MFG:456 Package Cooled:IDT D/C:

IDT74FCT162344CTPA, IDT74FCT162344ET, IDT74FCT162371CTPA Picture

IDT74FCT162344CTPA, IDT74FCT162344ET, IDT74FCT162371CTPA Datasheet download

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Part Number: IDT74FCT162344CTPA

MFG: 456

Package Cooled: IDT

D/C:

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IDT74FCT162344ET General Description

The FCT162344T is a 1:4 address/clock driver built using advanced dual metal CMOS technology. This high-speed, low power device provides the ability to fanout to memory arrays. Eight banks, each with a fanout of 4, and 3-state control provide efficient address distribution. One or more banks may be used for clock distribution.

The FCT162344T has balanced output drive with current limiting resistors. This offers low ground bounce, minimal undershoot and controlled output fall times reducing the need for external series terminating resistors. A large number of power and ground pins and TTL output swings also ensure reduced noise levels. All inputs are designed with hysteresis for improved noise margins.

IDT74FCT162344ET Maximum Ratings

Symbol	Description	Max	Unit
VTERM⁽²⁾	Terminal Voltage with Respect to GND	0.5 to +7	V
VTERM⁽³⁾	Terminal Voltage with Respect to GND	0.5 to V_CC+0.5	V
TSTG	Storage Temperature	65 to +150	°C
IOUT	DC Output Current	60 to +120	mA

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Output and I/O terminals terminals for FCT162XXX.

IDT74FCT162344ET Features

• 0.5 MICRON CMOS Technology
• Ideal for address line driving and clock distribution
• 8 banks with 1:4 fanout and 3-state
• Typical tSK(o) (Output Skew) < 500ps
• Balanced Output Drivers (±24mA)
• Reduced system switching noise
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
• VCC = 5V ± 10%
• Low input and output leakage 1A (max.)
• Available in SSOP and TSSOP packages

IDT74FCT162344ET Connection Diagram

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