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IDT74ALVCH16721, IDT74ALVCH16760, IDT74ALVCH16820PF

Table of contents:
Info of IDT74ALVCH16721
Info of IDT74ALVCH16760
Info of IDT74ALVCH16820PF

IDT74ALVCH16721, IDT74ALVCH16760, IDT74ALVCH16820PF Selling Leads, Datasheet

MFG:N/A Package Cooled:N/A D/C:09+

IDT74ALVCH16721, IDT74ALVCH16760, IDT74ALVCH16820PF Picture

IDT74ALVCH16721, IDT74ALVCH16760, IDT74ALVCH16820PF Datasheet download

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Part Number: IDT74ALVCH16721

MFG: N/A

Package Cooled: N/A

D/C: 09+

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IDT74ALVCH16721 General Description

This 20-bit flip-flop is built using advanced dual metal CMOS technology. The 20 flip-flops of the ALVCH16721 are edge-triggered D-type flip-flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs if the clock-enable (CLKEN) input is low. If CLKEN is high, no data is stored.

A buffered output-enable (OE) input places the 20 outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The highimpedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The ALVCH16721 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.

The ALVCH16721 has “bus-hold” which retains the inputs’ last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistor.

IDT74ALVCH16721 Maximum Ratings

Description	Symbol	Max	unit
Terminal Voltage with Respect to GND	VTERM⁽²⁾	–0.5 to +4.6	V
Terminal Voltage with Respect to GND	VTERM⁽³⁾	–0.5 to V_CC+0.5	V
Storage Temperature	T_STG	–65 to +150	° C
DC Output Current	I_OUT	–50 to +50	mA
Continuous Clamp Current, VI < 0 or VI > V_CC	I_IK	±50	mA
Continuous Clamp Current, V_O< 0	I_OK	–50	mA
Continuous Current through each V_CC or G_ND	I_CC I_SS	±100	mA

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.

IDT74ALVCH16721 Features

• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP, TSSOP, and TVSOP packages

IDT74ALVCH16721 Typical Application

• 3.3V high speed systems
• 3.3V and lower voltage computing systems

IDT74ALVCH16721 Connection Diagram

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