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IDT74ALVCH1660PA, IDT74ALVCH16646, IDT74ALVCH16652

Table of contents:
Info of IDT74ALVCH1660PA
Info of IDT74ALVCH16646
Info of IDT74ALVCH16652

IDT74ALVCH1660PA, IDT74ALVCH16646, IDT74ALVCH16652 Selling Leads, Datasheet

MFG:IDT Package Cooled:SSOP D/C:08+/09+

IDT74ALVCH1660PA, IDT74ALVCH16646, IDT74ALVCH16652 Picture

IDT74ALVCH1660PA, IDT74ALVCH16646, IDT74ALVCH16652 Datasheet download

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Part Number: IDT74ALVCH1660PA

MFG: IDT

Package Cooled: SSOP

D/C: 08+/09+

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IDT74ALVCH16646 General Description

This 16-bit bus transceiver is built using advanced dual metal CMOS technology. The ALVCH16646 can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Output-enable (OE ) and direction-control (DIR) inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or both.

The select control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. DIR determines which bus receives data when OE is low. In the isolation mode (OE high), A data may be stored in one register and/or B data may be stored in the other register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, can be driven at a time.

The ALVCH16646 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.

The ALVCH16646 has "bus-hold" which retains the inputs' last state whenever the input bus goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.

IDT74ALVCH16646 Maximum Ratings

Description	Symbol	Max	unit
Terminal Voltage with Respect to GND	VTERM⁽²⁾	0.5 to +4.6	V
Terminal Voltage with Respect to GND	VTERM⁽³⁾	0.5 to V_CC+0.5	V
Storage Temperature	T_STG	65 to +150	° C
DC Output Current	I_OUT	50 to +50	mA
Continuous Clamp Current, VI < 0 or VI > V_CC	I_IK	±50	mA
Continuous Clamp Current, V_O< 0	I_OK	50	mA
Continuous Current through each V_CC or G_ND	I_CC I_SS	±100	mA

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.

IDT74ALVCH16646 Features

• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP, TSSOP, and TVSOP packages

IDT74ALVCH16646 Typical Application

• 3.3V high speed systems
• 3.3V and lower voltage computing systems

IDT74ALVCH16646 Connection Diagram

IDT74ALVCH16652 General Description

This 16-bit bus transceiver and register is built using advanced dual metal CMOS technology. The ALVCH16652 consists of D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. The device can be used as two 8-bit transceivers or one 16-bit transceiver.

Complementary output enable (OEAB and OEBA) inputs are provided to control the transceiver functions. Select control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. A low input level selects real-time data, and a high input level selects stored data. Circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transition at the appropriate clock (CLKAB or CLKBA) inputs regardless of the levels on the select control or output enable inputs. When SAB and SBA are in the real-time transfer mode, it also is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are in the high-impedance state, each set of bus lines remains at its last level configuration.

The ALVCH16652 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. The ALVCH16652 has "bus-hold" which retains the inputs' last state whenever the input bus goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.

IDT74ALVCH16652 Maximum Ratings

Description	Symbol	Max	unit
Terminal Voltage with Respect to GND	VTERM⁽²⁾	0.5 to +4.6	V
Terminal Voltage with Respect to GND	VTERM⁽³⁾	0.5 to V_CC+0.5	V
Storage Temperature	T_STG	65 to +150	° C
DC Output Current	I_OUT	50 to +50	mA
Continuous Clamp Current, VI < 0 or VI > V_CC	I_IK	±50	mA
Continuous Clamp Current, V_O< 0	I_OK	50	mA
Continuous Current through each V_CC or G_ND	I_CC I_SS	±100	mA

IDT74ALVCH16652 Features

IDT74ALVCH16652 Typical Application

• 3.3V high speed systems
• 3.3V and lower voltage computing systems

IDT74ALVCH16652 Connection Diagram

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