MFG:IDT Package Cooled:TSSOP D/C:08+
IDT74ALVCH16525PA, IDT74ALVCH16540APF, IDT74ALVCH16601 Datasheet download
MFG: IDT
Package Cooled: TSSOP
D/C: 08+
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PDF/DataSheet Download
Datasheet: IDT 79R3081
File Size: 914564 KB
Manufacturer: IDT
Download : Click here to Download
PDF/DataSheet Download
Datasheet: IDT 79R3081
File Size: 914564 KB
Manufacturer: IDT
Download : Click here to Download
PDF/DataSheet Download
Datasheet: IDT74ALVCH16601
File Size: 75526 KB
Manufacturer: IDT
Download : Click here to Download
This 18-bit universal bus transceiver is built using advanced dual metal CMOS technology. The ALVCH16601 combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the data is stored in the latch/flip-flop on the lowto- high transition of CLKAB.
Output enable OEAB is active low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the highimpedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA and CLKENBA.
The ALVCH16601 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.
The ALVCH16601 has "bus-hold" which retains the inputs' last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.
|
Description |
Symbol |
Max |
unit |
|
Terminal Voltage with Respect to GND |
VTERM(2) |
0.5 to +4.6
|
V |
|
Terminal Voltage with Respect to GND |
VTERM(3)
|
0.5 to VCC+0.5 |
V |
|
Storage Temperature |
TSTG |
65 to +150
|
° C |
|
DC Output Current |
IOUT
|
50 to +50 |
mA |
|
Continuous Clamp Current, VI < 0 or VI > VCC |
IIK |
±50
|
mA |
|
Continuous Clamp Current, VO < 0 |
IOK |
50 |
mA |
|
Continuous Current through each VCC or GND |
ICC ISS |
±100 |
mA |
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.
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