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IDT74ALVCH16373APA, IDT74ALVCH16373PV, IDT74ALVCH16374

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Info of IDT74ALVCH16373APA
Info of IDT74ALVCH16373PV
Info of IDT74ALVCH16374

IDT74ALVCH16373APA, IDT74ALVCH16373PV, IDT74ALVCH16374 Selling Leads, Datasheet

MFG:IDT Package Cooled:TSSOP D/C:08+

IDT74ALVCH16373APA, IDT74ALVCH16373PV, IDT74ALVCH16374 Picture

IDT74ALVCH16373APA, IDT74ALVCH16373PV, IDT74ALVCH16374 Datasheet download

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Part Number: IDT74ALVCH16373APA

MFG: IDT

Package Cooled: TSSOP

D/C: 08+

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IDT74ALVCH16374 General Description

This 16-bit edge-triggered D-type flip-flop is built using advanced dual metal CMOS technology. The ALVCH16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels at the data (D) inputs. OE can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The highimpedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The ALVCH16374 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.

The ALVCH16374 has "bus-hold" which retains the inputs' last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistor.

IDT74ALVCH16374 Maximum Ratings

Symbol	Description	Max	Unit
VTERM(2)	Terminal Voltage with Respect to GND	0.5 to +4.6	V
VTERM(3)	Terminal Voltage with Respect to GND	0.5 to V_CC+0.5	V
T_STG	Storage Temperature	65 to +150
I_OUT	DC Output Current	50 to +50	mA
I_IK	Continuous Clamp Current, VI < 0 or VI > V_CC	±50	mA
I_OK	Continuous Clamp Current, VO < 0	50	mA
I_CC I_SS	Continuous Current through each V_CCor GND	±100	mA

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except V_CC.

IDT74ALVCH16374 Features

• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP, TSSOP, and TVSOP packages

IDT74ALVCH16374 Typical Application

• 3.3V high speed systems
• 3.3V and lower voltage computing systems

IDT74ALVCH16374 Connection Diagram

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