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IDT74ALVCH162245PF, IDT74ALVCH162268, IDT74ALVCH162373

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Info of IDT74ALVCH162245PF
Info of IDT74ALVCH162268
Info of IDT74ALVCH162373

IDT74ALVCH162245PF, IDT74ALVCH162268, IDT74ALVCH162373 Selling Leads, Datasheet

MFG:210 Package Cooled:IDT D/C:N/A

IDT74ALVCH162245PF, IDT74ALVCH162268, IDT74ALVCH162373 Picture

IDT74ALVCH162245PF, IDT74ALVCH162268, IDT74ALVCH162373 Datasheet download

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Part Number: IDT74ALVCH162245PF

MFG: 210

Package Cooled: IDT

D/C: N/A

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IDT74ALVCH162373 General Description

This 16-bit transparent D-type latch is built using advanced dual metal CMOS technology. The ALVCH162373 is particularly suitable for imple-menting buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one16-bit latch. When the latch enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (OE) can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.

The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be enetered while the outputs are in the high-impedance state.

The ALVCH162373 has series resistors in the device output structure which will significantly reduce line noise when used with light loads. This driver has been designed to drive ±12mA at the designated threshold levels. The ALVCH162373 has "bus-hold" which retains the inputs' last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistor.

IDT74ALVCH162373 Maximum Ratings

Symbol	Description	Max	Unit
V_TERM(2)	Terminal Voltage with Respect to GND	0.5 to +4.6	V
V_TERM(3)	Terminal Voltage with Respect to GND	0.5 to V_CC+0.5	V
T_STG	Storage Temperature	65 to +150	°C
I_OUT	DC Output Current	50 to +50	mA
I_IK	Continuous Clamp Current,VI < 0 or VI > VCC	±50	mA
I_OK	Continuous Clamp Current, VO < 0	50	mA
I_CC I_SS	Continuous Current through each VCC or GND	±100	mA

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.

IDT74ALVCH162373 Features

• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4 W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP and TSSOP packages

IDT74ALVCH162373 Typical Application

• 3.3V high speed systems
• 3.3V and lower voltage computing systems

IDT74ALVCH162373 Connection Diagram

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