Want to post a buying lead? If you are not a member yet, please select the specific/related part number first and then fill the quantity and your contact details in the "Request for Quotation Form" on the left, and then click "Send RFQ".Your buying lead can then be posted, and the reliable suppliers will quote via our online message system or other channels soon.
The IDT72V805/72V815/72V825/72V835/72V845 are dual 18-bit-wide synchronous (clocked) First-in, First-out (FIFO) memories designed to run off a 3.3V supply for exceptionally low power consumption. One dual DT72V805/72V815/72V825/72V835/72V845 device is functionally equivalent to two DT72V205/72V215/72V225/72V235/72V245 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins. These devices are very high-speed, low-power First-In, First-Out (FIFO) memories with clocked read and write controls. These FIFOs are applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs contained in these devices has an 18-bit input and output port. Each input port is controlled by a free-running clock (WCLK), and an input enable pin (WEN). Data is read into the synchronous FIFO on every clock when WEN is asserted. The output port of each FIFO bank is controlled by another clock pin (RCLK) and another enable pin (REN). The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation. An Output Enable pin (OE) is provided on the read port of each FIFO for three-state control of the output.
The synchronous FIFOs have two fixed flags, Empty Flag/Output Ready (EF/OR) and Full Flag/Input Ready (FF/IR), and two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF). The offset loading of the programmable flags is controlled by a simple state machine, and is initiated by asserting the Load pin (LD). A Half-Full flag (HF) is available for each FIFO that is implemented as a single device.
There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through (FWFT) mode. In IDT Standard Mode, the first word written to an empty FIFO will not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN and enabling a rising RCLK edge, will shift the word from internal memory to the data output lines.
In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A REN does not have to be asserted for accessing the first word.
These devices are depth expandable using a Daisy-Chain technique or First Word Fall Through (FWFT) mode. The XI and XO pins are used to expand the FIFOs. In depth expansion configuration, FL is grounded on the first device and set to HIGH for all other devices in the Daisy Chain. The IDT72V805/72V815/72V825/72V835/72V845 are fabricated using IDT's high-speed submicron CMOS technology.
IDT72V825 Maximum Ratings
Symbol
Rating
Commercial &Industrial
Unit
VTERM
Terminal Voltage with Respect to GND
0.5 to +5
V
TSTG
Storage Temperature
-55 to +125
oC
IOUT
DC Output Current
-55 to +50
mA
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
IDT72V825 Features
` The IDT72V805 is equivalent to two IDT72V205 256 x 18 FIFOs ` The IDT72V815 is equivalent to two IDT72V215 512 x 18 FIFOs ` The IDT72V825 is equivalent to two IDT72V225 1,024 x 18 FIFOs ` The IDT72V835 is equivalent to two IDT72V235 2,048 x 18 FIFOs ` The IDT72V845 is equivalent to two IDT72V245 4,096 x 18 FIFOs ` Offers optimal combination of large capacity (8K), high speed, design flexibility, and small footprint ` Ideal for the following applications: Network switching Two level prioritization of parallel data Bidirectional data transfer Bus-matching between 18-bit and 36-bit data paths Width expansion to 36-bit per package Depth expansion to 8,192 words per package ` 10 ns read/write cycle time ` 5V input tolerant ` IDT Standard or First Word Fall Through timing ` Single or double register-buffered Empty and Full Flags ` Easily expandable in depth and width ` Asynchronous or coincident Read and Write Clocks ` Asynchronous or synchronous programmable Almost-Empty and Almost-Full flags with default settings ` Half-Full flag capability ` Output enable puts output data bus in high-impedance state ` High-performance submicron CMOS technology ` Available in a 128-pin thin quad flatpack (TQFP) ` Industrial temperature range (40°C to +85°C) is available