IDT72V51553, IDT72V51556, IDT72V547 Selling Leads, Datasheet
MFG:IDT Package Cooled:N/A D/C:09+
IDT72V51553, IDT72V51556, IDT72V547 Datasheet download
Part Number: IDT72V51553
MFG: IDT
Package Cooled: N/A
D/C: 09+
IDT72V51553, IDT72V51556, IDT72V547
- Table of contents:
Info of IDT72V51553
Info of IDT72V51556
Info of IDT72V547
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About IDT72V51553
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Datasheet: IDT72V51553
File Size: 488810 KB
Manufacturer: IDT
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About IDT72V51556
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Datasheet: IDT72V51556
File Size: 568787 KB
Manufacturer: IDT
Download : Click here to Download
About IDT 79R3081
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Datasheet: IDT 79R3081
File Size: 914564 KB
Manufacturer: IDT
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IDT72V51553 General Description
The IDT72V51543/72V51553 multi-queue flow-control devices are single chip within which anywhere between 1 and 32 discrete FIFO queues can be setup. All queues within the device have a common data input bus, (write port) and a common data output bus, (read port).
Data written into the write port is directed to a respective queue via an internal de-multiplex operation, addressed by the user. Data read from the read port is accessed from a respective queue via an internal multiplex operation, addressed by the user. Data writes and reads can be performed at high speeds up to 166MHz, with access times of 3.7ns. Data write and read operations are totally independent of each other, a queue maybe selected on the write port and a different queue on the read port or both ports may select the same queue simultaneously.
The device provides Full flag and Output Valid flag status for the queue selected for write and read operations respectively. Also a Programmable Almost Full and Programmable Almost Empty flag for each queue is provided. Two 8 bit programmable flag busses are available, providing status of queues not selected for write or read operations. When 8 or less queues are configured in the device these flag busses provide an individual flag per queue, when more than 8 queues are used, either a Polled or Direct mode of bus operation wide. When Bus Matching is used the device ensures the logical transfer of data throughput in a Little Endian manner.
The user has full flexibility configuring queues within the device, being able to program the total number of queues between 1 and 32, the individual queue depths being independent of each other.
The programmable flag positions are also user programmable. All programming is done via a dedicated serial port. If the user does not wish to program the multi-queue device, a default option is available that configures the device in a predetermined manner. Both Master Reset and Partial Reset pins are provided on this device. A Master Reset latches in all configuration setup pins and must be performed before programming of the device can take place. A Partial Reset will reset the read and write pointers of an individual queue, provided that the queue is selected on both the write port and read port at the time of partial reset.
A JTAG test port is provided, here the multi-queue flow-control device has a fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. See Figure 1, Multi-Queue Flow-Control Device Block Diagram for an outline of the functional blocks within the device.
IDT72V51553 Maximum Ratings
|
Symbol |
Rating |
Com'l & Ind'l
|
Unit |
|
VTERM |
Terminal Voltage with respect to GND |
0.5 to +4.5 |
V |
|
TSTG |
Storage Temperature |
55 to +125 |
°C |
|
IOUT |
DC Output Current |
50 to +50
|
mA |
IDT72V51553 Features
• Choose from among the following memory density options:
IDT72V51543 Total Available Memory = 1,179,648 bits
IDT72V51553 Total Available Memory = 2,359,296 bits
• Configurable from 1 to 32 Queues
• 166 MHz High speed operation (6ns cycle time)
• 3.7ns access time
• Queues may be configured at master reset from the pool of
Total Available Memory in blocks of 512 x 18 or 1,024 x 9
• Independent Read and Write access per queue
• User programmable via serial port
• Default multi-queue device configurations
-IDT72V51543: 2,048 x 18 x 32Q or 4,096 x 9 x 32Q
-IDT72V51553: 4,096 x 18 x 32Q or 8,192 x 9 x 32Q
• 100% Bus Utilization, Read and Write on every clock cycle
• Individual, Active queue flags (OV, FF, PAE, PAF)
• 8 bit parallel flag status on both read and write ports
• Direct or polled operation of flag status bus
• Global Bus Matching - (All Queues have same Input Bus Width
and Output Bus Width)
• User Selectable Bus Matching Options:
- x18in to x18out
- x9in to x18out
- x18in to x9out
- x9in to x9out
• FWFT mode of operation on read port
• Partial Reset, clears data in single Queue
• Expansion of up to 8 multi-queue devices in parallel is available
• JTAG Functionality (Boundary Scan)
• Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm
• HIGH Performance submicron CMOS technology
• Industrial temperature range (-40°C to +85°C) is available
IDT72V51543 Total Available Memory = 1,179,648 bits
IDT72V51553 Total Available Memory = 2,359,296 bits
• Configurable from 1 to 32 Queues
• 166 MHz High speed operation (6ns cycle time)
• 3.7ns access time
• Queues may be configured at master reset from the pool of
Total Available Memory in blocks of 512 x 18 or 1,024 x 9
• Independent Read and Write access per queue
• User programmable via serial port
• Default multi-queue device configurations
-IDT72V51543: 2,048 x 18 x 32Q or 4,096 x 9 x 32Q
-IDT72V51553: 4,096 x 18 x 32Q or 8,192 x 9 x 32Q
• 100% Bus Utilization, Read and Write on every clock cycle
• Individual, Active queue flags (OV, FF, PAE, PAF)
• 8 bit parallel flag status on both read and write ports
• Direct or polled operation of flag status bus
• Global Bus Matching - (All Queues have same Input Bus Width
and Output Bus Width)
• User Selectable Bus Matching Options:
- x18in to x18out
- x9in to x18out
- x18in to x9out
- x9in to x9out
• FWFT mode of operation on read port
• Partial Reset, clears data in single Queue
• Expansion of up to 8 multi-queue devices in parallel is available
• JTAG Functionality (Boundary Scan)
• Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm
• HIGH Performance submicron CMOS technology
• Industrial temperature range (-40°C to +85°C) is available
IDT72V51556 General Description
The IDT72V51546/72V51556 multi-queue flow-control devices are single chip within which anywhere between 1 and 32 discrete FIFO queues can be setup. All queues within the device have a common data input bus, (write port) and a common data output bus, (read port). Data written into the write port is directed to a respective queue via an internal de-multiplex operation, addressed by the user.
Data read from the read port is accessed from a respective queue via an internal multiplex operation, addressed by the user. Data writes and reads can be performed at high speeds up to 166MHz, with access times of 3.7ns. Data write and read operations are totally independent of each other, a queue maybe selected on the write port and a different queue on the read port or both ports may select the same queue simultaneously.
The device provides Full flag and Output Valid flag status for the queue selected for write and read operations respectively. Also a Programmable Almost Full and Programmable Almost Empty flag for each queue is provided. Two 8 bit programmable flag busses are available, providing status of queues not selected for write or read operations. When 8 or less queues are configured in the device these flag busses provide an individual flag per queue, when more than 8 queues are used, either a Polled or Direct mode of bus operation provides the flag busses with all queues status.
Bus Matching is available on this device, either port can be 9 bits, 18 bits or 36 bits wide provided that at least one port is 36 bits wide. When Bus Matching is used the device ensures the logical transfer of data throughput in a Little with a flag output indicating when at least one (or more) packets of data within a queue is available for reading. The Packet Ready provides the user with a means by which to mark the start and end of packets of data being passed through the queues. The multi-queue device then provides the user with an internally generated packet ready status per queue. The user has full flexibility configuring queues within the device, being able to program the total number of queues between 1 and 32, the individual queue depths being independent of each other. The programmable flag positions are also user programmable.
All programming is done via a dedicated serial port. If the user does not wish to program the multi-queue device, a default option is available that configures the device in a predetermined manner. Both Master Reset and Partial Reset pins are provided on this device. A Master Reset latches in all configuration setup pins and must be performed before programming of the device can take place. A Partial Reset will reset the read and write pointers of an individual queue, provided that the queue is selected on both the write port and read port at the time of partial reset.
A JTAG test port is provided, here the multi-queue flow-control device has a fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. See Figure 1, Multi-Queue Flow-Control Device Block Diagram for an outline of the functional blocks within the device.
IDT72V51556 Maximum Ratings
|
Symbol |
Rating |
Com'l & Ind'l
|
Unit |
|
VTERM |
Terminal Voltage with respect to GND |
0.5 to +4.5 |
V |
|
TSTG |
Storage Temperature |
55 to +125 |
°C |
|
IOUT |
DC Output Current |
50 to +50
|
mA |
IDT72V51556 Features
• Choose from among the following memory density options:
IDT72V51546 Total Available Memory = 1,179,648 bits
IDT72V51556 Total Available Memory = 2,359,296 bits
• Configurable from 1 to 32 Queues
• Queues may be configured at master reset from the pool of
Total Available Memory in blocks of 256 x 36
• Independent Read and Write access per queue
• User programmable via serial port
• Default multi-queue device configurations
IDT72V51546 : 1,024 x 36 x 32Q
IDT72V51556 : 2,048 x 36 x 32Q
• 100% Bus Utilization, Read and Write on every clock cycle
• 166 MHz High speed operation (6ns cycle time)
• 3.7ns access time
• Individual, Active queue flags (OV, FF, PAE, PAF, PR)
• 8 bit parallel flag status on both read and write ports
• Shows PAE and PAF status of 8 Queues
• Global Bus Matching - (All Queues have same Input Bus Width
and Output Bus Width)
• User Selectable Bus Matching Options:
x36in to x36out
x18in to x36out
x9in to x36out
x36in to x18out
x36in to x9out
• FWFT mode of operation on read port
• Packet mode operation
• Partial Reset, clears data in single Queue
• Expansion of up to 8 multi-queue devices in parallel is available
• JTAG Functionality (Boundary Scan)
• Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm
• HIGH Performance submicron CMOS technology
• Industrial temperature range (-40°C to +85°C) is available
IDT72V51546 Total Available Memory = 1,179,648 bits
IDT72V51556 Total Available Memory = 2,359,296 bits
• Configurable from 1 to 32 Queues
• Queues may be configured at master reset from the pool of
Total Available Memory in blocks of 256 x 36
• Independent Read and Write access per queue
• User programmable via serial port
• Default multi-queue device configurations
IDT72V51546 : 1,024 x 36 x 32Q
IDT72V51556 : 2,048 x 36 x 32Q
• 100% Bus Utilization, Read and Write on every clock cycle
• 166 MHz High speed operation (6ns cycle time)
• 3.7ns access time
• Individual, Active queue flags (OV, FF, PAE, PAF, PR)
• 8 bit parallel flag status on both read and write ports
• Shows PAE and PAF status of 8 Queues
• Global Bus Matching - (All Queues have same Input Bus Width
and Output Bus Width)
• User Selectable Bus Matching Options:
x36in to x36out
x18in to x36out
x9in to x36out
x36in to x18out
x36in to x9out
• FWFT mode of operation on read port
• Packet mode operation
• Partial Reset, clears data in single Queue
• Expansion of up to 8 multi-queue devices in parallel is available
• JTAG Functionality (Boundary Scan)
• Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm
• HIGH Performance submicron CMOS technology
• Industrial temperature range (-40°C to +85°C) is available
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