IDT72V3673, IDT72V3674, IDT72V3676 Selling Leads, Datasheet
MFG:IDT Package Cooled:N/A D/C:09+
IDT72V3673, IDT72V3674, IDT72V3676 Datasheet download
Part Number: IDT72V3673
MFG: IDT
Package Cooled: N/A
D/C: 09+
IDT72V3673, IDT72V3674, IDT72V3676
- Table of contents:
Info of IDT72V3673
Info of IDT72V3674
Info of IDT72V3676
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About IDT72V3673
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Datasheet: IDT72V3673
File Size: 466559 KB
Manufacturer: IDT
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About IDT72V3674
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Datasheet: IDT72V3674
File Size: 615348 KB
Manufacturer: IDT
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About IDT72V3676
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Datasheet: IDT72V3676
File Size: 626683 KB
Manufacturer: IDT
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IDT72V3673 General Description
The IDT72V3653/72V3663/72V3673 are pin and functionally compatible versions of the IDT723653/723663/723673, designed to run off a 3.3V supply for exceptionally low power consumption. These devices are monolithic, highspeed, low-power, CMOS unidirectional Synchronous (clocked) FIFO memory which supports clock frequencies up to 100 MHz and has read access times as fast as 6.5 ns. The 2,048/4,096/8,192 x 36 dual-port SRAM FIFO buffers data from Port A to Port B. FIFO data on Port B can output in 36-bit, 18-bit, or 9-bit formats with a choice of Big- or Little-Endian configurations. These devices are synchronous (clocked) FIFOs, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
IDT72V3673 Maximum Ratings
| Symbol | Rating | Commercial | Unit |
| VCC | Supply Voltage Range | 0.5 to +4.6 | V |
| VI(2) | Input Voltage Range | 0.5 to VCC+0.5 | V |
| VO(2) | Output Voltage Range | 0.5 to VCC+0.5 | V |
| IIK | Input Clamp Current (VI < 0 or VI > VCC) | ±20 | mA |
| IOK | Output Clamp Current (VO = < 0 or VO > VCC) | ±50 | mA |
| IOUT | Continuous Output Current (VO = 0 to VCC) | ±50 | mA |
| ICC | Continuous Current Through VCC or GND | ±400 | mA |
| TSTG | Storage Temperature Range | 65 to 150 | °C |
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
IDT72V3673 Features
` Memory storage capacity:
IDT72V3653 2,048 x 36
IDT72V3663 4,096 x 36
IDT72V3673 8,192 x 36
` Clock frequencies up to 100 MHz (6.5 ns access time)
` Clocked FIFO buffering data from Port A to Port B
` IDT Standard timing (using EF and FF) or First Word Fall
Through Timing (using OR and IR flag functions)
` Programmable Almost-Empty and Almost-Full flags; each has
five default offsets (8, 16, 64, 256 and 1,024)
` Serial or parallel programming of partial flags
` Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits (byte)
` Big- or Little-Endian format for word and byte bus sizes
` Retransmit Capability
` Reset clears data and configures FIFO, Partial Reset clears data
but retains configuration settings
` Mailbox bypass registers for each FIFO
` Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
` Easily expandable in width and depth
` Auto power down minimizes power dissipation
` Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
` Pin and functionally compatible versions of the 5V operating
IDT723653/723663/723673
` Pin compatible with the lower density parts, IDT72V3623/
72V3633/72V3643
` Industrial temperature range (40°C to +85°C) is available
IDT72V3653 2,048 x 36
IDT72V3663 4,096 x 36
IDT72V3673 8,192 x 36
` Clock frequencies up to 100 MHz (6.5 ns access time)
` Clocked FIFO buffering data from Port A to Port B
` IDT Standard timing (using EF and FF) or First Word Fall
Through Timing (using OR and IR flag functions)
` Programmable Almost-Empty and Almost-Full flags; each has
five default offsets (8, 16, 64, 256 and 1,024)
` Serial or parallel programming of partial flags
` Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits (byte)
` Big- or Little-Endian format for word and byte bus sizes
` Retransmit Capability
` Reset clears data and configures FIFO, Partial Reset clears data
but retains configuration settings
` Mailbox bypass registers for each FIFO
` Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
` Easily expandable in width and depth
` Auto power down minimizes power dissipation
` Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
` Pin and functionally compatible versions of the 5V operating
IDT723653/723663/723673
` Pin compatible with the lower density parts, IDT72V3623/
72V3633/72V3643
` Industrial temperature range (40°C to +85°C) is available
IDT72V3673 Connection Diagram
IDT72V3674 General Description
The IDT72V3654/72V3664/72V3674 are pin and functionally compat-ible versions of the IDT723654/723664/723674, designed to run off a 3.3V supply for exceptionally low-power consumption. These devices are mono-lithic, high-speed, low-power, CMOS bidirectional synchronous (clocked) FIFO memory which supports clock frequencies up to 100 MHz and has read access times as fast as 6.5ns. Two independent 2,048/4,096/8,192 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. FIFO data on Port B can be input and output in 36-bit, 18-bit, or 9-bit formats with a choice of Big- or Little-Endian configurations.
These devices are a synchronous (clocked) FIFO, meaning each portemploys a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or
IDT72V3674 Maximum Ratings
| Symbol | Rating | Commercial | Unit |
| VCC | Supply Voltage Range | 0.5 to +4.6 | V |
| VI(2) | Input Voltage Range | 0.5 to VCC +0.5 | V |
| VO(2) | Output Voltage Range | 0.5 to VCC +0.5 | V |
| IIK | Input Clamp Current (VI< 0 or VI> VCC) | ±20 | mA |
| IOK | Output Clamp Current (VO= < 0 or VO> VCC) | ±50 | mA |
| IOUT | Continuous Output Current (VO= 0 to VCC) | ±50 | mA |
| ICC |
Continuous Current Through VCC or GND | ±400 | mA |
| TSTG | Storage Temperature Range | 65 to 150 |
IDT72V3674 Features
Memory storage capacity:IDT72V36542,048 x 36 x 2 IDT72V36644,096 x 36 x 2 IDT72V36644,096 x 36 x 2
Clock frequencies up to 100 MHz (6.5ns access time)
Two independent clocked FIFOs buffering data in opposite directions
Select IDT Standard timing (using EFA EFB FFA , and FFB flags functions) or First Word Fall Through Timing (using ORA, ORB,IRA, and IRB flag functions)
Programmable Almost-Empty and Almost-Full flags; each has five default offsets (8, 16, 64, 256 and 1,024 )
Serial or parallel programming of partial flags
Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits(byte)
Big- or Little-Endian format for word and byte bus sizes
Retransmit Capability
Master Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA and CLKB may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted)
Auto power down minimizes power dissipation
Available in space saving 128-pin Thin Quad Flatpack (TQFP)
Pin and functionally compatible version of the 5V operating IDT723654/723664/723674
Pin compatible to the lower density parts, IDT72V3624/72V3634/72V3644
Industrial temperature range (40°C to +85°C) is available
IDT72V3674 Connection Diagram
IDT72V3676 General Description
The IDT72V3656/72V3666/72V3676 are pin and functionally compatible versions of the IDT723626/723636/723646, designed to run off a 3.3V supply for exceptionally low-power consumption. These devices are a monolithic, high-speed, low-power, CMOS Triple Bus synchronous (clocked) FIFO memory which supports clock frequencies up to 100 MHz and has read access times as fast as 6.5ns. Two independent 2,048/4,096/8,192 x 36 dual-portSRAM FIFOs on board each chip buffer data between a bidirectional 36-bit bus (Port A) and two unidirectional 18-bit buses (Port B transmits data, Port C receives data.) FIFO data can be read out of Port B and written into Port C using either 18-bit or 9-bit formats with a choice of Big- or Little-Endian configurations.
These devices are a synchronous (clocked) FIFO, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
IDT72V3676 Maximum Ratings
| Symbol | Rating | Commercial | Unit |
| VCC | Supply Voltage Range | 0.5 to +4.6 | V |
| VI(2) | Input Voltage Range | 0.5 to VCC+0.5 | V |
| VO(2) | Output Voltage Range | 0.5 to VCC+0.5 | V |
| IIK | Input Clamp Current (VI < 0 or VI > VCC) | ±20 | mA |
| IOK | Output Clamp Current (VO = < 0 or VO > VCC) | ±50 | mA |
| IOUT | Continuous Output Current (VO = 0 to VCC) | ±50 | mA |
| ICC | Continuous Current Through VCC or GND | ±400 | mA |
| TSTG | Storage Temperature Range | 65 to 150 | °C |
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
IDT72V3676 Features
` Memory storage capacity:
IDT72V3656 2,048 x 36 x 2
IDT72V3666 4,096 x 36 x 2
IDT72V3676 8,192 x 36 x 2
` Clock frequencies up to 100 MHz (6.5ns access time)
` Two independent FIFOs buffer data between one bidirectional
36-bit port and two unidirectional 18-bit ports (Port C receives
and Port B transmits)
` 18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on Ports B and C
` Select IDT Standard timing (using EFA , EFB , FFA , and FFC flag
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRC flag functions)
` Programmable Almost-Empty and Almost-Full flags; each has
five default offsets (8, 16, 64, 256 and 1,024)
` Serial or parallel programming of partial flags
` Big- or Little-Endian format for word and byte bus sizes
` Loopback mode on Port A
` Retransmit Capability
` Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
` Mailbox bypass registers for each FIFO
` Free-running CLKA, CLKB and CLKC may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
` Auto power down minimizes power dissipation
` Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
` Pin and functionally compatible versions of the 5V parts,
IDT723656/723666/723676
` Pin compatible to the lower density parts, IDT72V3626/3636/3646
` Industrial temperature range (40°C to +85°C) is available
IDT72V3656 2,048 x 36 x 2
IDT72V3666 4,096 x 36 x 2
IDT72V3676 8,192 x 36 x 2
` Clock frequencies up to 100 MHz (6.5ns access time)
` Two independent FIFOs buffer data between one bidirectional
36-bit port and two unidirectional 18-bit ports (Port C receives
and Port B transmits)
` 18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on Ports B and C
` Select IDT Standard timing (using EFA , EFB , FFA , and FFC flag
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRC flag functions)
` Programmable Almost-Empty and Almost-Full flags; each has
five default offsets (8, 16, 64, 256 and 1,024)
` Serial or parallel programming of partial flags
` Big- or Little-Endian format for word and byte bus sizes
` Loopback mode on Port A
` Retransmit Capability
` Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
` Mailbox bypass registers for each FIFO
` Free-running CLKA, CLKB and CLKC may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
` Auto power down minimizes power dissipation
` Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
` Pin and functionally compatible versions of the 5V parts,
IDT723656/723666/723676
` Pin compatible to the lower density parts, IDT72V3626/3636/3646
` Industrial temperature range (40°C to +85°C) is available
IDT72V3676 Connection Diagram
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