IDT72V221L20JI, IDT72V221L20PFI, IDT72V223 Selling Leads, Datasheet
MFG:IDT Package Cooled:QFP D/C:0633+?
IDT72V221L20JI, IDT72V221L20PFI, IDT72V223 Datasheet download
Part Number: IDT72V221L20JI
MFG: IDT
Package Cooled: QFP
D/C: 0633+?
IDT72V221L20JI, IDT72V221L20PFI, IDT72V223
- Table of contents:
Info of IDT72V221L20JI
Info of IDT72V221L20PFI
Info of IDT72V223
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About IDT72V221L20JI
PDF/DataSheet Download
Datasheet: IDT72V221L20JI
File Size: 118182 KB
Manufacturer: IDT [Integrated Device Technology]
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About IDT72V221L20PFI
PDF/DataSheet Download
Datasheet: IDT72V221L20PFI
File Size: 118182 KB
Manufacturer: IDT [Integrated Device Technology]
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About IDT72V223
PDF/DataSheet Download
Datasheet: IDT72V223
File Size: 444686 KB
Manufacturer: IDT
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IDT72V223 General Description
•The IDT72V223/72V233/72V243/72V253/72V263/72V273/72V283/ 72V293 are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls and a flexible Bus-Matching x9/ x18 data flow. These FIFOs offer numerous improvements over previous SuperSync FIFOs, including the following: Flexible x9/x18 Bus-Matching on both read and write ports The limitation of the frequency of one clock input with respect to the other has been removed. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency.
• The period required by the retransmit operation is now fixed and short.
• The first word data latency period, from the time the first word is written to an empty FIFO to the time it can be read, is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSync family.)
• Asynchronous/Synchronous translation on the read or write ports
• High density offerings up to 1 Mbit
Bus-Matching SuperSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.
• The period required by the retransmit operation is now fixed and short.
• The first word data latency period, from the time the first word is written to an empty FIFO to the time it can be read, is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSync family.)
• Asynchronous/Synchronous translation on the read or write ports
• High density offerings up to 1 Mbit
Bus-Matching SuperSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.
IDT72V223 Maximum Ratings
| Symbol | Rating | Com’l & Ind’l | Unit |
| VTERM(2) |
Terminal Voltage with respect to GND |
–0.5 to +4.5 | V |
| TSTG | Storage Temperature | –55 to +125 | °C |
| IOUT | DC Output Current | –50 to +50 | mA |
IDT72V223 Features
* Choose among the following memory organizations:
IDT72V223 512 x 18/1,024 x 9
IDT72V233 1,024 x 18/2,048 x 9
IDT72V243 2,048 x 18/4,096 x 9
IDT72V253 4,096 x 18/8,192 x 9
IDT72V263 8,192 x 18/16,384 x 9
IDT72V273 16,384 x 18/32,768 x 9
IDT72V283 32,768 x 18/65,536 x 9
IDT72V293 65,536 x 18/131,072 x 9
* Functionally compatible with the IDT72V255LA/72V265LA and IDT72V275/72V285 SuperSync FIFOs
* Up to 166 MHz Operation of the Clocks
* User selectable Asynchronous read and/or write ports (BGA Only)
* User selectable input and output port bus-sizing
- x9 in to x9 out
- x9 in to x18 out
- x18 in to x9 out
- x18 in to x18 out
* Pin to Pin compatible to the higher density of IDT72V2103/72V2113
* Big-Endian/Little-Endian user selectable byte representation
* 5V tolerant inputs
IDT72V223 512 x 18/1,024 x 9
IDT72V233 1,024 x 18/2,048 x 9
IDT72V243 2,048 x 18/4,096 x 9
IDT72V253 4,096 x 18/8,192 x 9
IDT72V263 8,192 x 18/16,384 x 9
IDT72V273 16,384 x 18/32,768 x 9
IDT72V283 32,768 x 18/65,536 x 9
IDT72V293 65,536 x 18/131,072 x 9
* Functionally compatible with the IDT72V255LA/72V265LA and IDT72V275/72V285 SuperSync FIFOs
* Up to 166 MHz Operation of the Clocks
* User selectable Asynchronous read and/or write ports (BGA Only)
* User selectable input and output port bus-sizing
- x9 in to x9 out
- x9 in to x18 out
- x18 in to x9 out
- x18 in to x18 out
* Pin to Pin compatible to the higher density of IDT72V2103/72V2113
* Big-Endian/Little-Endian user selectable byte representation
* 5V tolerant inputs
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