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IDT72815LB, IDT72815LB10BG, IDT72815LB10PF

Table of contents:
Info of IDT72815LB
Info of IDT72815LB10BG
Info of IDT72815LB10PF

IDT72815LB, IDT72815LB10BG, IDT72815LB10PF Selling Leads, Datasheet

MFG:IDT, Integrated Device Technology Inc Category:Undefined Category Package Cooled:N/A D/C:09+

IDT72815LB, IDT72815LB10BG, IDT72815LB10PF Picture

IDT72815LB, IDT72815LB10BG, IDT72815LB10PF Datasheet download

Five Points

Part Number: IDT72815LB

Category: Undefined Category

MFG: IDT, Integrated Device Technology Inc

Package Cooled: N/A

D/C: 09+

Description: IC FIFO SYNC DUAL 512X18 128TQFP

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IDT72815LB General Description

The IDT72805LB/72815LB/72825LB/72835LB/72845LB are dual 18-bit-wide synchronous (clocked) First-in, First-out (FIFO) memories. One dual IDT72805LB/ 72815LB/72825LB/72835LB/72845LB device is functionally equivalent to two IDT72205LB/72215LB/72225LB/72235LB/72245LB FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins. These devices are very high-speed, low-power First-In, First-Out (FIFO) memories with clocked read and write controls. These FIFOs are applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication.

Each of the two FIFOs contained in these devices has an 18-bit input and output port. Each input port is controlled by a free-running clock (WCLK), and an input enable pin (WEN). Data is read into the synchronous FIFO on every clock when WEN is asserted. The output port of each FIFO bank is controlled by another clock pin (RCLK) and another enable pin (REN). The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. An Output Enable pin (OE) is provided on the read port of each FIFO for three-state control of the output.

The synchronous FIFOs have two fixed flags, Empty Flag/Output Ready (EF/OR) and Full Flag/Input Ready (FF/IR), and two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF). The offset loading of the programmableflags is controlled by a simple state machine, and is initiated by asserting the Load pin (LD). A Half-Full flag (HF) is available for each FIFO that is implemented as a single device configuration.

There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through (FWFT) mode.

In IDT Standard Mode, the first word written to an empty FIFO will not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN and enabling a rising RCLK edge, will shift the word from internal memory to the data output lines.

In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A REN does not have to be asserted for accessing the first word.

These devices are depth expandable using a daisy-chain technique or First Word Fall Through (FWFT) mode. The XI and XO pins are used to expand the FIFOs. In depth expansion configuration, FL is grounded on the first device and set to HIGH for all other devices in the Daisy Chain.

The IDT72805LB/72815LB/72825LB/72835LB/72845LB are fabricated using IDT's high-speed submicron CMOS technology.

IDT72815LB Maximum Ratings

Symbol	Rating	Commercial &Industrial	Unit
V_TERM	Terminal Voltage with Respect to GND	0.5 to +7.0	V
T_STG	Storage Temperature	-55 to +125	oC
I_OUT	DC Output Current	-55 to +50	mA

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

IDT72815LB Features

• The IDT72805LB is equivalent to two IDT72205LB 256 x 18 FIFOs
• The IDT72815LB is equivalent to two IDT72215LB 512 x 18 FIFOs
• The IDT72825LB is equivalent to two IDT72225LB 1,024 x 18 FIFOs
• The IDT72835LB is equivalent to two IDT72235LB 2,048 x 18 FIFOs
• The IDT72845LB is equivalent to two IDT72245LB 4,096 x 18 FIFOs
• Offers optimal combination of large capacity (8K), high speed, design flexibility, and small footprint
• Ideal for the following applications: - Network switching - Two level prioritization of parallel data - Bidirectional data transfer - Bus-matching between 18-bit and 36-bit data paths - Width expansion to 36-bit per package - Depth expansion to 8,192 words per package
• 10ns read/write cycle time, 6.5ns access time
• IDT Standard or First Word Fall Through timing
• Single or double register-buffered Empty and Full Flags
• Easily expandable in depth and width
• Asynchronous or coincident Read and Write clocks
• Asynchronous or synchronous programmable Almost-Empt and Almost-Full flags with default settings
• Half-Full flag capability
• Output Enable puts output data bus in high-impedance state
• High-performance submicron CMOS technology
• Available in the 128-pin Thin Quad Flatpack (TQFP). Also available for the IDT72805LB/72815LB/72825LB, in the 121-lead,16 x 16 mm plastic Ball Grid Array (PBGA)
• Industrial temperature range (40°C to +85°C) is available

IDT72815LB Connection Diagram

IDT72815LB10PF Parameters

Technical/Catalog Information	IDT72815LB10PF
Vendor	IDT, Integrated Device Technology Inc
Category	Undefined Category
Lead Free Status	Contains Lead
RoHS Status	RoHS Non-Compliant
Other Names	IDT72815LB10PF IDT72815LB10PF

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