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IDT71V3559S85PFI, IDT71V3559SA, IDT71V3561S200BG

Table of contents:
Info of IDT71V3559S85PFI
Info of IDT71V3559SA
Info of IDT71V3561S200BG

IDT71V3559S85PFI, IDT71V3559SA, IDT71V3561S200BG Selling Leads, Datasheet

MFG:IDT, Integrated Device Technology Inc Category:Integrated Circuits (ICs) Package Cooled:IDT D/C:05+

IDT71V3559S85PFI, IDT71V3559SA, IDT71V3561S200BG Picture

IDT71V3559S85PFI, IDT71V3559SA, IDT71V3561S200BG Datasheet download

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Part Number: IDT71V3559S85PFI

Category: Integrated Circuits (ICs)

MFG: IDT, Integrated Device Technology Inc

Package Cooled: IDT

D/C: 05+

Description: IC SRAM 256KX18 85NS 100-TQFP

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IDT71V3559S85PFI Parameters

Technical/Catalog Information	IDT71V3559S85PFI
Vendor	IDT, Integrated Device Technology Inc
Category	Integrated Circuits (ICs)
Memory Type	SRAM - Synchronous ZBT
Memory Size	4M (256K x 18)
Speed	85ns
Interface	Parallel
Package / Case	100-TQFP
Packaging	Tray
Voltage - Supply	3.135 V ~ 3.465 V
Operating Temperature	-40°C ~ 85°C
Format - Memory	RAM
Drawing Number	*
Lead Free Status	Contains Lead
RoHS Status	RoHS Non-Compliant
Other Names	IDT71V3559S85PFI IDT71V3559S85PFI

IDT71V3559SA General Description

The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or Zero Bus Turnaround.

Address and control signals are applied to the SRAM during one clock cycle, and on the next clock cycle the associated data cycle occurs, be it read or write.

The IDT71V3557/59 contain address, data-in and control signal registers. The outputs are flow-through (no output data register). Output enable is the only asynchronous signal and can be used to disable the outputs at any given time.

A Clock Enable (CEN) pin allows operation of the IDT71V3557/59 to be suspended as long as necessary. All synchronous inputs are ignored when (CEN) is high and the internal device registers will hold their previous values.

There are three chip enable pins (CE₁, CE₂, CE₂) that allow the user to deselect the device when desired. If any one of these three is not asserted when ADV/LD is low, no new memory operation can be initiated. However, any pending data transfers (reads or writes) will be completed. The data bus will tri-state one cycle after chip is deselected or a write is initiated.

The IDT71V3557/59 have an on-chip burst counter. In the burst mode, the IDT71V3557/59 can provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by theLBO input pin. TheLBO pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address (ADV/LD = LOW) or increment the internal burst counter (ADV/LD = HIGH).

The IDT71V3557/59 SRAMs utilize IDT's latest high-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA) and a 165 fine pitch ball grid array (fBGA).

IDT71V3559SA Maximum Ratings

Symbol	Rating	Commercial & Industrial	Unit
V_TERM⁽²⁾	Terminal Voltage with Respect to GND	-0.5 to +4.6	V
V_TERM^(3,6)	Terminal Voltage with Respect to GND	-0.5 to V_DD	V
V_TERM^(4,6)	Terminal Voltage with Respect to GND	-0.5 to V_DD +0.5	V
V_TERM^(5,6)	Terminal Voltage with Respect to GND	-0.5 to V_DDQ +0.5	V
T_A⁽⁷⁾	Commercial Operating Temperature	-0 to +70
T_A⁽⁷⁾	Industrial Operating Temperature	-40 to +85
T_BIAS	Temperature Under Bias	55 to +125
T_STG	Storage Temperature	55 to +125
P_T	Power Dissipation	2.0	W
I_OUT	DC Output Current	50	mA

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. V_DD terminals only.
3. V_DDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has reached its nominal operating value. Power sequencing is not necessary;however, the voltage on any input or I/O pin cannot exceed V_DDQ during power
supply ramp up.
7. T_A is the "instant on" case temperature.

IDT71V3559SA Features

· 128K x 36, 256K x 18 memory configurations
· Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access)
· ZBT^TM Feature - No dead cycles between write and read cycles
· Internally synchronized output buffer enable eliminates the need to control OE· Single R/W (READ/WRITE) control pin
· 4-word burst capability (Interleaved or linear)
· Individual byte write (BW1 - BW4) control (May tie active)
· Three chip enables for simple depth expansion
· 3.3V power supply (±5%), 3.3V (±5%) I/O Supply (V_DDQ)
· Optional Boundary Scan JTAG Interface (IEEE 1149.1 complaint)
· Packaged in a JEDEC Standard 100-pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array (fBGA)

IDT71V3559SA Connection Diagram

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