IDT70V99S, IDT70V99S10PF, IDT70V9L Selling Leads, Datasheet
MFG:N/A Package Cooled:N/A D/C:09+
IDT70V99S, IDT70V99S10PF, IDT70V9L Datasheet download
Part Number: IDT70V99S
MFG: N/A
Package Cooled: N/A
D/C: 09+
MFG:N/A Package Cooled:N/A D/C:09+
IDT70V99S, IDT70V99S10PF, IDT70V9L Datasheet download
MFG: N/A
Package Cooled: N/A
D/C: 09+
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PDF/DataSheet Download
Datasheet: IDT 79R3081
File Size: 914564 KB
Manufacturer: IDT
Download : Click here to Download
PDF/DataSheet Download
Datasheet: IDT 79R3081
File Size: 914564 KB
Manufacturer: IDT
Download : Click here to Download
PDF/DataSheet Download
Datasheet: IDT 79R3081
File Size: 914564 KB
Manufacturer: IDT
Download : Click here to Download
The IDT70V3319/99 is a high-speed 256/128K x 18 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70V3319/99 has been optimized for applications having unidirectionalor bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode.
The 70V3319/99 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) remains at 3.3V.
Symbol | Rating | Commercial & Industrial |
Unit |
VTERM(2) |
Terminal Voltage with Respect to GND |
-0.5 to +4.6 | V |
TBIAS(3) |
Temperature Under Bias | -55 to +125 | |
TSTG | Storage Temperature | -65 to +150 | |
TJN | Junction Temperature | +150 | |
IOUT | DC Output Current | 50 | mA |
True Dual-Port memory cells which allow simultaneous access of the same memory location
High-speed data access Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.) Industrial: 4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode Due to limited pin count PL/FT option is not supported on the 128-pin TQFP package. Device is pipelined outputs only on each port.
Counter enable and repeat features
Dual chip enables allow for depth expansion without additional logic
Full synchronous operation on both ports 6ns cycle time, 166MHz operation (6Gbps bandwidth) Fast 3.6ns clock to data out 1.7ns setup to clockand 0.5ns hold on all control, data, and address inputs @ 166MHz