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IDT70V7519S133BC, IDT70V7589S, IDT70V7599S

Table of contents:
Info of IDT70V7519S133BC
Info of IDT70V7589S
Info of IDT70V7599S

IDT70V7519S133BC, IDT70V7589S, IDT70V7599S Selling Leads, Datasheet

MFG:IDT, Integrated Device Technology Inc Category:Integrated Circuits (ICs) Package Cooled:BGA-256P D/C:03+

IDT70V7519S133BC, IDT70V7589S, IDT70V7599S Picture

IDT70V7519S133BC, IDT70V7589S, IDT70V7599S Datasheet download

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Part Number: IDT70V7519S133BC

Category: Integrated Circuits (ICs)

MFG: IDT, Integrated Device Technology Inc

Package Cooled: BGA-256P

D/C: 03+

Description: IC RAM 9MBIT DUAL 133MHZ 256-BGA

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IDT70V7519S133BC Parameters

Technical/Catalog Information	IDT70V7519S133BC
Vendor	IDT, Integrated Device Technology Inc
Category	Integrated Circuits (ICs)
Memory Type	SRAM - Dual Port, Synchronous
Memory Size	9M (256K x 36)
Speed	133MHz
Interface	Parallel
Package / Case	256-BGA
Packaging	Tray
Voltage - Supply	3.15 V ~ 3.45 V
Operating Temperature	0°C ~ 70°C
Format - Memory	RAM
Drawing Number	*
Lead Free Status	Contains Lead
RoHS Status	RoHS Non-Compliant
Other Names	IDT70V7519S133BC IDT70V7519S133BC

IDT70V7589S General Description

The IDT70V7589 is a high-speed 64Kx36 (2Mbit) synchronousBank-Switchable Dual-Ported SRAM organized into 64 independent1Kx36 banks. The device has two independent ports with separatecontrol, address, and I/O pins for each port, allowing each port to accessany 1Kx36 memory block not already accessed by the other port.Accesses by the ports into specific banks are controlled via the bankaddress pins under the user's direct control.

Registers on control, data, and address inputs provide minimal setupand hold times. The timing latitude provided by this approach allowssystems to be designed with very short cycle times. With an input data register, the IDT70V7589 has been optimized for applications havingunidirectional or bidirectional data flow in bursts. An automatic power downfeature, controlled by CE₀ and CE₁, permits the on-chip circuitry of eachport to enter a very low standby power mode. The dual chip enables alsofacilitate depth expansion.

The 70V7589 can support an operating voltage of either 3.3V or 2.5Von one or both ports, controllable by the OPT pins. The power supply forthe core of the device(V_DD) remains at 3.3V. Please refer also to thefunctional description on page 19.

IDT70V7589S Maximum Ratings

Symbol	Rating	Commercial & Industrial	Unit
V_TERM⁽²⁾	Terminal Voltage with Respect to GND	-0.5 to +4.6	V
T_BIAS	Temperature Under Bias	55 to +125
T_STG	Storage Temperature	65 to +150
I_OUT	DC Output Current	50	mA

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. V_TERM must not exceed V_DD + 150mV for more than 25% of the cycle time or4ns maximum, and is limited to 20mA for the period of V_TERM V_DD + 150mV.

IDT70V7589S Features

` 64K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture 64 independent 1K x 36 banks
   - 2 megabits of memory on chip
` Bank access controlled via bank address pins
` High-speed data access
   -Commercial: 3.4ns (200MHz)/3.6ns (166MHz)/4.2ns (133MHz) (max.)
   -Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
` Selectable Pipelined or Flow-Through output mode
` Counter enable and repeat features
` Dual chip enables allow for depth expansion without additional logic
` Full synchronous operation on both ports
   -5ns cycle time, 200MHz operation (14Gbps bandwidth)
   -Fast 3.4ns clock to data out
   - 1.5ns setup to clock and 0.5ns hold on all control, data, and address inputs @ 200MHz
Data input, address, byte enable and control registers
Self-timed write allows fast cycle time
`Separate byte controls for multiplexed bus and bus matching compatibility
`LVTTL- compatible, 3.3V (±150mV) power supply for core
` LVTTL compatible, selectable 3.3V (±150mV) or 2.5V ±100mV)(±100mV) power supply for I/Os and control signals on
each port
` Industrial temperature range (-40°C to +85°C) is available at 166MHz and 133MHz
`Available in a 208-pin Plastic Quad Flatpack (PQFP),208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball
Grid Array (BGA)
` Supports JTAG features compliant with IEEE 1149.1

IDT70V7589S Connection Diagram

IDT70V7599S General Description

The IDT70V7599 is a high-speed 128Kx36 (4Mbit) synchronous Bank-Switchable Dual-Ported SRAM organized into 64 independent 2Kx36 banks. The device has two independent ports with separate control, address, and I/O pins for each port, allowing each port to access any 2Kx36 memory block not already accessed by the other port. Accesses by the ports into specific banks are controlled via the bank address pins under the user's direct control.

Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70V7599 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE₀and CE₁, permits the on-chip circuitry of each port to enter a very low standby power mode. The dual chip enables also acilitate depth expansion.

The 70V7599 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device(VDD) remains at 3.3V. Please refer also to the functional description on page 19.

IDT70V7599S Maximum Ratings

Symbol	Rating	Commercial & Industrial	Unit
V_TERM⁽²⁾	Terminal Voltage with Respect to GND	0.5 to +4.6	V
T_BIAS	Temperature Under Bias	55 to +125
T_STG	Storage Temperature	60 to +150
I_OUT	DC Output Current	50	mA

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. V_TERM must not exceed V_DD + 150mV for more than 25% of the cycle time or 4ns maximum, and is limited to 20mA for the period of V_TERMV_DD + 150mV.

IDT70V7599S Features

` 128K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture
   64 independent 2K x 36 banks
   4 megabits of memory on chip
` Bank access controlled via bank address pins
` High-speed data access
   Commercial: 3.4ns (200MHz)/3.6ns (166MHz)/4.2ns (133MHz) (max.)
   Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
` Selectable Pipelined or Flow-Through output mode
` Counter enable and repeat features
` Dual chip enables allow for depth expansion without additional logic
` Full synchronous operation on both ports
   5ns cycle time, 200MHz operation (14Gbps bandwidth)
   Fast 3.4ns clock to data out
   1.5ns setup to clock and 0.5ns hold on all control, data, and address inputs @ 200MHz
   Data input, address, byte enable and control registers
   Self-timed write allows fast cycle time
` Separate byte controls for multiplexed bus and bus matching compatibility
` LVTTL- compatible, 3.3V (±150mV) power supply for core
` LVTTL compatible, selectable 3.3V (±150mV) or 2.5V (±100mV) power supply for I/Os and control signals on each port
` Industrial temperature range (-40°C to +85°C) is available at 166MHz and 133MHz
` Available in a 208-pin Plastic Quad Flatpack (PQFP), 208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball Grid Array (BGA)
`Supports JTAG features compliant with IEEE 1149.1

IDT70V7599S Connection Diagram

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