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IDT70V04S25PF, IDT70V05-25PF, IDT70V05L

Table of contents:
Info of IDT70V04S25PF
Info of IDT70V05-25PF
Info of IDT70V05L

IDT70V04S25PF, IDT70V05-25PF, IDT70V05L Selling Leads, Datasheet

MFG:IDT Package Cooled:TQFP D/C:0

IDT70V04S25PF, IDT70V05-25PF, IDT70V05L Picture

IDT70V04S25PF, IDT70V05-25PF, IDT70V05L Datasheet download

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Part Number: IDT70V04S25PF

MFG: IDT

Package Cooled: TQFP

D/C: 0

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IDT70V05L General Description

The IDT70V05 is a high-speed 8K x 8 Dual-Port Static RAM. The IDT70V05 is designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/SLAVE DualPort RAM for 16-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider
memory system applications results in full-speed, error-free operation without the need for additional discrete logic.

This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled byCE permits the on-chip circuitry of each port to enter a very low
standby power mode.

Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 350mW of power.Low-power (L) versions offer battery backup data retention capability with typical power consumption of 500µW from a 2V battery.

The IDT70V05 is packaged in a ceramic 68-pin PGA, a 68-pin PLCC, and a 64-pin thin plastic quad flatpack (TQFP).

IDT70V05L Maximum Ratings

Symbol	Rating	Commercial	Unit
VTER⁽²⁾	Terminal Voltage with Respect to GND	0.5 to +4.6	V
T^A	Operating Temperature	0 to +70	°C
T^BIAS	Temperature Under Bias	55 to +125	°C
T^STG	Storage Temperature	55 to +125	°C
I^OUT	DC Output Current	50	mA

NOTES: 2941 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 0.3V.

IDT70V05L Features

• True Dual-Ported memory cells which allow simulta-
   neous access of the same memory location
• High-speed access
   - Commercial: 25/35/55ns (max.)
• Low-power operation
   - IDT70V05S
       Active: 350mW (typ.)
       Standby: 3.5mW (typ.)
   - IDT70V05L
       Active: 350mW (typ.)
       Standby: 1mW (typ.)
• IDT70V05 easily expands data bus width to 16 bits or
   more using the Master/Slave select when cascading
   more than one device
• M/S = H for BUSY output flag on Master
   M/S = L for BUSY input on Slave
• Busy and Interrupt Flags
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
   between ports
• Fully asynchronous operation from either port
• Devices are capable of withstanding greater than 2001V
   electrostatic discharge
• Battery backup operation-2V data retention
• LVTTL-compatible, single 3.3V (±0.3V) power supply
• Available in 68-pin PGA, 68-pin PLCC, and a 64-pin
   TQFP

IDT70V05L Connection Diagram

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