HIP6502CB-T, HIP6503, HIP6503C3CBP Selling Leads, Datasheet
MFG:Intersil Package Cooled:Original D/C:04+05+
HIP6502CB-T, HIP6503, HIP6503C3CBP Datasheet download
Part Number: HIP6502CB-T
MFG: Intersil
Package Cooled: Original
D/C: 04+05+
HIP6502CB-T, HIP6503, HIP6503C3CBP
- Table of contents:
Info of HIP6502CB-T
Info of HIP6503
Info of HIP6503C3CBP
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About HIP0045
PDF/DataSheet Download
Datasheet: HIP0045
File Size: 95776 KB
Manufacturer: INTERSIL [Intersil Corporation]
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About HIP6503
PDF/DataSheet Download
Datasheet: HIP6503
File Size: 155011 KB
Manufacturer: INTERSIL [Intersil Corporation]
Download : Click here to Download
About HIP0045
PDF/DataSheet Download
Datasheet: HIP0045
File Size: 95776 KB
Manufacturer: INTERSIL [Intersil Corporation]
Download : Click here to Download
HIP6503 General Description
The HIP6503 complements either an HIP6020 or an HIP6021 in ACPI-compliant designs for microprocessor and computer applications. The IC integrates four linear controllers/regulators, switching, monitoring and control functions into a 20 pin SOIC package. One linear controller generates the 3.3VDUAL/3.3VSB voltage plane from the ATX supply's 5VSB output, powering the south bridge and the PCI slots through an external pass transistor during sleep states (S3, S4/S5). A second transistor is used to switch in the ATX 3.3V output for operation during S0 and S1/S2 (active) operating states. A linear controllers/regulator supplies at choice either of 2.5V or 3.3V memory power through external pass transistors (switch for 3.3V setting) in active states. During sleep states, integrated pass transistors supply the sleep power. Another controller powers up the 5VDUAL plane by switching in the ATX 5V output in active states, and the ATX 5VSB in sleep states.
Two internal regulators output both a dedicated, noise-free 2.5V clock chip supply, as well as a 1.8V ICH2 resume well voltage. The HIP6503's operating mode (active outputs or sleep outputs) is selectable through two digital control pins, S3 and S5. Enabling sleep state support on the 5VDUAL output is offered through the EN5VDL pin. In active state, the 3.3VDUAL/3.3VSB and 2.5VMEM/3.3VMEM linear regulators use external N-channel pass MOSFETs to connect the outputs directly to the 3.3V input supplied by an ATX power supply, for minimal losses. In sleep state, power delivery on both outputs is transferred to NPN transistors - external to the controller on the 3.3VDUAL/3.3VSB, internal on the 2.5VMEM/3.3VMEM. Active state regulation on the 2.5VMEM output is performed through an external NPN transistor. The 5VDUAL output is powered through two external MOS transistors. In sleep states, a PMOS (or PNP) transistor conducts the current from the ATX 5VSB output; while in active state, current flow is transferred to an NMOS transistor connected to the ATX 5V output. The operation of the 5VDUAL output is dictated not only by the status of the S3 and S5 pins, but that of the EN5VDL pin as well. The 3.3VDUAL/3.3VSB and 1.8VSB outputs are active for as long as the ATX 5VSB voltage is applied to the chip. The 2.5VCLK output is only active during S0 and S1/S2, and uses the 3V3 pin as input source for its internal pass element.
Two internal regulators output both a dedicated, noise-free 2.5V clock chip supply, as well as a 1.8V ICH2 resume well voltage. The HIP6503's operating mode (active outputs or sleep outputs) is selectable through two digital control pins, S3 and S5. Enabling sleep state support on the 5VDUAL output is offered through the EN5VDL pin. In active state, the 3.3VDUAL/3.3VSB and 2.5VMEM/3.3VMEM linear regulators use external N-channel pass MOSFETs to connect the outputs directly to the 3.3V input supplied by an ATX power supply, for minimal losses. In sleep state, power delivery on both outputs is transferred to NPN transistors - external to the controller on the 3.3VDUAL/3.3VSB, internal on the 2.5VMEM/3.3VMEM. Active state regulation on the 2.5VMEM output is performed through an external NPN transistor. The 5VDUAL output is powered through two external MOS transistors. In sleep states, a PMOS (or PNP) transistor conducts the current from the ATX 5VSB output; while in active state, current flow is transferred to an NMOS transistor connected to the ATX 5V output. The operation of the 5VDUAL output is dictated not only by the status of the S3 and S5 pins, but that of the EN5VDL pin as well. The 3.3VDUAL/3.3VSB and 1.8VSB outputs are active for as long as the ATX 5VSB voltage is applied to the chip. The 2.5VCLK output is only active during S0 and S1/S2, and uses the 3V3 pin as input source for its internal pass element.
HIP6503 Maximum Ratings
Supply Voltage, V5VSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
12V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to +14.5V
DLA, DRV2. . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to V12V +0.3V
All Other Pins . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5VSB + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3
12V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to +14.5V
DLA, DRV2. . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to V12V +0.3V
All Other Pins . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5VSB + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3
HIP6503 Features
• Provides 5 ACPI-Controlled Voltages
- 5VDUAL USB/Keyboard/Mouse (Active/Sleep)
- 3.3VDUAL/3.3VSB PCI/Auxiliary/LAN (Active/Sleep)
- 2.5VMEM RDRAM or 3.3VMEM SDRAM (Active/Sleep)
- 2.5VCLK Clock/Processor Terminations (Active Only)
- 1.8VSB ICH2 Resume
• Excellent Output Voltage Regulation
- 3.3VDUAL/3.3VSB Output: ±2.0% Over Temperature; Sleep State Only
- 2.5VMEM/3.3VMEM Output: ±2.0% Over Temperature; Both Operational States (3.3VMEM in sleep only)
- 1.8VSB, 2.5VCLK Outputs: ±2.0% Over Temperature
• Small Size
- Very Low External Component Count
• Dual Memory Voltage Selection Via FAULT/MSEL Pin
- 2.5V for RDRAM Memory
- 3.3V for SDRAM Memory
• Undervoltage Monitoring of All Outputs with Centralized FAULT Reporting and Temperature Shutdown
- 5VDUAL USB/Keyboard/Mouse (Active/Sleep)
- 3.3VDUAL/3.3VSB PCI/Auxiliary/LAN (Active/Sleep)
- 2.5VMEM RDRAM or 3.3VMEM SDRAM (Active/Sleep)
- 2.5VCLK Clock/Processor Terminations (Active Only)
- 1.8VSB ICH2 Resume
• Excellent Output Voltage Regulation
- 3.3VDUAL/3.3VSB Output: ±2.0% Over Temperature; Sleep State Only
- 2.5VMEM/3.3VMEM Output: ±2.0% Over Temperature; Both Operational States (3.3VMEM in sleep only)
- 1.8VSB, 2.5VCLK Outputs: ±2.0% Over Temperature
• Small Size
- Very Low External Component Count
• Dual Memory Voltage Selection Via FAULT/MSEL Pin
- 2.5V for RDRAM Memory
- 3.3V for SDRAM Memory
• Undervoltage Monitoring of All Outputs with Centralized FAULT Reporting and Temperature Shutdown
HIP6503 Typical Application
• Motherboard Power Regulation for ACPI-Compliant Computers
HIP6503 Connection Diagram
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