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These dual N-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary,high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for digital transistors in load switching applications. Since bias resistors are not required this one N-Channel FET can replace several digital transistors with different bias resistors like the IMHxA series.
FDC6303N Maximum Ratings
Symbol
Parameter
FDC6304P
Units
VDSS
Drain-Source Voltage, Power Supply Voltage
25
V
VGSS
Gate-Source Voltage,
8
V
ID, IO
Drain Current - Continuous
- Pulsed
0.68
A
2
PD
Maximum Power Dissipation (Note 1a)
(Note1b)
0.9
W
0.7
TJ, Tstg
Operating and Storage Tempature Ranger
-55 to +150
°C
ESD
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
6.0
kV
FDC6303N Features
25 V, 0.68 Acontinuous, -0.5 A Peak. R DS(ON)= 0.6 W @ VGS= -2.7 V R DS(ON) = 0.45W@ VGS= -4.5 V Very low level gate drive requirements allowing direct operation in 3V circuits. V GS(th)<1.5V. Gate-Source Zener for ESD ruggedness.>6kV Human Body Model Replace multiple PNP digital transistors (IMHxA series) with one DMOS FET.