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EDS1232AASE-75L-E, EDS1232AATA, EDS1232AATA-60

Table of contents:
Info of EDS1232AASE-75L-E
Info of EDS1232AATA
Info of EDS1232AATA-60

EDS1232AASE-75L-E, EDS1232AATA, EDS1232AATA-60 Selling Leads, Datasheet

MFG:ELPIDA Package Cooled:BGA D/C:05+

EDS1232AASE-75L-E, EDS1232AATA, EDS1232AATA-60 Picture

EDS1232AASE-75L-E, EDS1232AATA, EDS1232AATA-60 Datasheet download

Five Points

Part Number: EDS1232AASE-75L-E

MFG: ELPIDA

Package Cooled: BGA

D/C: 05+

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EDS1232AATA General Description

The EDS1232AA is a 128M bits SDRAM organized as 1,048,576 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock.

They are packaged in 90-ball FBGA, 86-pin plastic TSOP (II).

EDS1232AATA Maximum Ratings

Parameter	Symbol	Rating	Unit
Voltage on any pin relative to VSS	VT	0.5 to +4.6	V
Supply voltage relative to VSS	VDD, VDDQ	0.5 to +4.6	V
Short circuit output current	IOS	50	mA
Power dissipation	PD	1.0	W
Operating temperature	TA	0 to +70	°C
Storage temperature	Tstg	55 to +125	°C

Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.

EDS1232AATA Features

• 3.3V power supply
• Clock frequency: 166MHz (max.)
• Single pulsed /RAS
• ×32 organization
• 4 banks can operate simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length (BL): 1, 2, 4, 8 and full page
• 2 variations of burst sequence
-Sequential (BL = 1, 2, 4, 8)
-Interleave (BL = 1, 2, 4, 8)
• Programmable /CAS latency (CL): 2, 3
• Byte control by DQM
• Refresh cycles: 4096 refresh cycles/64ms
• 2 variations of refresh
-Auto refresh
-Self refresh
• FBGA package is lead free solder (Sn-Ag-Cu)

EDS1232AATA Connection Diagram

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