Want to post a buying lead? If you are not a member yet, please select the specific/related part number first and then fill the quantity and your contact details in the "Request for Quotation Form" on the left, and then click "Send RFQ".Your buying lead can then be posted, and the reliable suppliers will quote via our online message system or other channels soon.
The CYP(V)15G0401DXB[1] Quad HOTLink II™ Transceiveris a point-to-point or point-to-multipoint communications building block allowing the transfer of data over high-speed serial links (optical fiber, balanced, and unbalanced copper transmission lines) at signaling speeds ranging from 195-to-1500 MBaud per serial link.
CYP15G0401DXB Maximum Ratings
Storage Temperature ..................................65°C to +150°C Ambient Temperature with Power Applied...55°C to +125°C Supply Voltage to Ground Potential ............... 0.5V to +3.8V DC Voltage Applied to LVTTL Outputs in High-Z State .......................................0.5V to VCC + 0.5V Output Current into LVTTL Outputs (LOW)....................60 mA DC Input Voltage.....................................0.5V to VCC + 0.5V Static Discharge Voltage.......................................... > 2000 V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA
CYP15G0401DXB Features
• Quad channel transceiver for 195 to 1500 MBaud serial signaling rate -Aggregate throughput of 12 GBits/second • Second-generation HOTLink® technology • Compliant to multiple standards -ESCON, DVB-ASI, Fibre Channel and Gigabit Ethernet (IEEE802.3z) -CYV15G0401DXB also compliant to SMPTE 259M and SMPTE 292M -8B/10B encoded or 10-bit unencoded data • Selectable parity check/generate • Selectable multi-channel bonding options -Four 8-bit channels -Two 16-bit channels -One 32-bit channel -N x 32-bit channel support (inter-chip) • Skew alignment support for multiple bytes of offset • Selectable input/output clocking options • MultiFrame™ Receive Framer -Bit and Byte alignment -Comma or full K28.5 detect -Single- or multi-byte framer for byte alignment -Low-latency option • Synchronous LVTTL parallel interface • Optional Elasticity Buffer in Receive Path • Optional Phase Align Buffer in Transmit Path • Internal phase-locked loops (PLLs) with no external PLL components • Dual differential PECL-compatible serial inputs per channel -Internal DC-restoration • Dual differential PECL-compatible serial outputs per channel -Source matched for 50Ω transmission lines -No external bias resistors required -Signaling-rate controlled edge-rates • Compatible with -fiber-optic modules -copper cables -circuit board traces • JTAG boundary scan • Built-In Self-Test (BIST) for at-speed link testing • Per-channel Link Quality Indicator -Analog signal detect -Digital signal detect • Low power 2.5W @ 3.3V typical • Single 3.3V supply • 256-ball thermally enhanced BGA • 0.25µ BiCMOS technology