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The CYP(V)15G0201DXB[1] Dual-channel HOTLink II™ Transceiver is a point-to-point or point-to-multipoint communications building block allowing the transfer of data over high-speed serial links (optical fiber, balanced, and unbalanced copper transmission lines) at signaling speeds ranging from 195- to 1500-MBaud per serial link.
The CYV15G0201DXB satisfies the SMPTE 259M and SMPTE 292M compliance as per the EG34-1999 Pathological Test Requirements.
CYP15G0201DXB Maximum Ratings
Storage Temperature ..............................................................65°C to +150°C Ambient Temperature with Power Applied................................55°C to +125°C Supply Voltage to Ground Potential .............................................. 0.5V to +3.8V DC Voltage Applied to LVTTL Outputs in High-Z State ............0.5V to VCC + 0.5V Output Current into LVTTL Outputs (LOW)....................................................60 mA DC Input Voltage....................................................................0.5V to VCC + 0.5V Static Discharge Voltage.......................................................................... > 2000 V (per MIL-STD-883, Method 3015) Latch-up Current................................ > 200 mA
CYP15G0201DXB Features
• Dual channel transceiver for 195 to 1500 MBaud serial signaling rate -Aggregate throughput of 12 GBits/second • Second-generation HOTLink® technology • Compliant to multiple standards -ESCON, DVB-ASI, Fibre Channel and Gigabit Ethernet (IEEE802.3z) -CYV15G0201DXB also compliant to SMPTE 259M and SMPTE 292M -8B/10B encoded or 10-bit unencoded data • Selectable parity check/generate • Selectable dual-channel bonding option -One 16-bit channels • Skew alignment support for multiple bytes of offset • Selectable input/output clocking options • MultiFrame™ Receive Framer -Bit and Byte alignment -Comma or full K28.5 detect -Single- or multi-byte framer for byte alignment -Low-latency option • Synchronous LVTTL parallel interface • Internal phase-locked loops (PLLs) with no external PLL components • Optional Phase-Align Buffer in transmit path • Optional Elasticity Buffer in receive path • Dual differential PECL-compatible serial inputs per channel -Internal DC-restoration • Dual differential PECL-compatible serial outputs per channel -Source matched for 50Ω transmission lines -No external bias resistors required -Signaling-rate controlled edge-rates • Compatible with -fiber-optic modules -copper cables -circuit board traces • JTAG boundary scan • Built-In Self-Test (BIST) for at-speed link testing • Per-channel Link Quality Indicator -Analog signal detect -Digital signal detect • Low power 1.8W @ 3.3V typical • Single 3.3V supply • 196-ball BGA • 0.25µ BiCMOS technology