CY3120, CY3120R61, CY3125 Selling Leads, Datasheet
MFG:CYPRESS Package Cooled:N/A D/C:09+
CY3120, CY3120R61, CY3125 Datasheet download
Part Number: CY3120
MFG: CYPRESS
Package Cooled: N/A
D/C: 09+
CY3120, CY3120R61, CY3125
- Table of contents:
Info of CY3120
Info of CY3120R61
Info of CY3125
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About CY3120
PDF/DataSheet Download
Datasheet: CY3120
File Size: 125205 KB
Manufacturer: Cypress
Download : Click here to Download
About CY30
PDF/DataSheet Download
Datasheet: CY30
File Size: 131545 KB
Manufacturer: ETC [ETC]
Download : Click here to Download
About CY3125
PDF/DataSheet Download
Datasheet: CY3125
File Size: 125205 KB
Manufacturer: Cypress
Download : Click here to Download
CY3120 General Description
Warp2 is a state-of-the-art HDL compiler for designing with Cypress's Complex Programmable Logic Devices (CPLDs). Warp2 utilizes a subset of IEEE 1076 and 1164 VHDL as its Hardware Description Language (HDL) for design entry. Warp2 accepts VHDL, synthesizes and optimizes the entered design, and outputs a JEDEC file for the desired PLD or CPLD (see Figure 1). Furthermore, Warp2 accepts VHDL produced by the Active-HDL FSM graphical Finite State Machine editor (PC only). For simulation, Warp2 provides a timing simulator (PC only), as well as VHDL and Verilog timing models for use with third party simulators.
CY3120 Features
• VHDL (IEEE 1076 and 1164) high-level language compiler
-Facilitates device-independent design
-Designs are portable across multiple devices and/or EDA environments
-Facilitates the use of industry-standard simulation and synthesis tools for board and system-level design
-Supports functions and libraries facilitating modular design methodology
• Warp2® provides synthesis of IEEE Standard 1076 and 1164 VHDL including:
-Enumerated types
-Operator overloading
-For ... Generate statements
-Integers
• Several design entry methods support high and low-level design descriptions:
-Behavioral VHDL (IF...THEN...ELSE; CASE...)
-Boolean
-Aldec Active-HDL™ FSM graphical Finite State Machine editor (PC only)
-Structural VHDL (RTL)
-Designs can include multiple VHDL entry methods in a single design
• State-of-the-art optimizations and reduction algorithms
-Automatic selection of optimal flip-flop type (D type/T type)
-Automatic pin assignment
• UltraGen™ Synthesis and Fitting Technology
-Infers "modules" like adders, comparators, etc., from behavioral descriptions
-Replaces operator internally with an architecture specific circuit based on the target device
-User selectable speed and/or area optimization on a block-by-block basis
• Supports all Cypress Programmable Logic Devices
-Ultra37000™ CPLDs (now with FBGA support)
-FLASH370i™ CPLDs
-MAX340™ CPLDs
-Industry standard PLDs (16V8, 20V8, 22V10)
• VHDL and Verilog timing model output for use with third-party simulators
• Timing simulation provided with Active-HDL™ Sim Release 3.3 from Aldec (PC only)
-Graphical waveform simulator
-Entry and modification of on-screen waveforms
-Ability to probe internal nodes
-Display of inputs, outputs, and High Impedance (Z) signals in different colors
-Automatic clock and pulse creation
-Support for buses
• Year 2000 Compliant
• PC Support (Windows 95™, Windows 98™ and Windows NT™ 4.0)
• Workstation Support including Sun Solaris™ and HP-UX™
• On-line documentation and help
CY3125 General Description
Warp2 is a state-of-the-art HDL compiler for designing with Cypress's Complex Programmable Logic Devices (CPLDs). Warp2 utilizes a subset of IEEE 1076 and 1164 VHDL as its Hardware Description Language (HDL) for design entry. Warp2 accepts VHDL, synthesizes and optimizes the entered design, and outputs a JEDEC file for the desired PLD or CPLD (see Figure 1). Furthermore, Warp2 accepts VHDL produced by the Active-HDL FSM graphical Finite State Machine editor (PC only). For simulation, Warp2 provides a timing simulator (PC only), as well as VHDL and Verilog timing models for use with third party simulators.
CY3125 Features
• VHDL (IEEE 1076 and 1164) high-level language compiler
-Facilitates device-independent design
-Designs are portable across multiple devices and/or EDA environments
-Facilitates the use of industry-standard simulation and synthesis tools for board and system-level design
-Supports functions and libraries facilitating modular design methodology
• Warp2® provides synthesis of IEEE Standard 1076 and 1164 VHDL including:
-Enumerated types
-Operator overloading
-For ... Generate statements
-Integers
• Several design entry methods support high and low-level design descriptions:
-Behavioral VHDL (IF...THEN...ELSE; CASE...)
-Boolean
-Aldec Active-HDL™ FSM graphical Finite State Machine editor (PC only)
-Structural VHDL (RTL)
-Designs can include multiple VHDL entry methods in a single design
• State-of-the-art optimizations and reduction algorithms
-Automatic selection of optimal flip-flop type (D type/T type)
-Automatic pin assignment
• UltraGen™ Synthesis and Fitting Technology
-Infers "modules" like adders, comparators, etc., from behavioral descriptions
-Replaces operator internally with an architecture specific circuit based on the target device
-User selectable speed and/or area optimization on a block-by-block basis
• Supports all Cypress Programmable Logic Devices
-Ultra37000™ CPLDs (now with FBGA support)
-FLASH370i™ CPLDs
-MAX340™ CPLDs
-Industry standard PLDs (16V8, 20V8, 22V10)
• VHDL and Verilog timing model output for use with third-party simulators
• Timing simulation provided with Active-HDL™ Sim Release 3.3 from Aldec (PC only)
-Graphical waveform simulator
-Entry and modification of on-screen waveforms
-Ability to probe internal nodes
-Display of inputs, outputs, and High Impedance (Z) signals in different colors
-Automatic clock and pulse creation
-Support for buses
• Year 2000 Compliant
• PC Support (Windows 95™, Windows 98™ and Windows NT™ 4.0)
• Workstation Support including Sun Solaris™ and HP-UX™
• On-line documentation and help
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