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ATR0622P1-PYQW, ATR0622P-PYQW, ATR0625

Table of contents:
Info of ATR0622P1-PYQW
Info of ATR0622P-PYQW
Info of ATR0625

ATR0622P1-PYQW, ATR0622P-PYQW, ATR0625 Selling Leads, Datasheet

MFG:Atmel Category:RF and RFID Package Cooled:QFN D/C:2010+

ATR0622P1-PYQW, ATR0622P-PYQW, ATR0625 Picture

ATR0622P1-PYQW, ATR0622P-PYQW, ATR0625 Datasheet download

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Part Number: ATR0622P1-PYQW

Category: RF and RFID

MFG: Atmel

Package Cooled: QFN

D/C: 2010+

Description: IC GPS BASE PROCESSOR 56-QFN

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ATR0622P-PYQW Parameters

Technical/Catalog Information	ATR0622P-PYQW
Vendor	Atmel
Category	RF and RFID
Function	GPS Baseband Processor
Secondary Attributes	SPI Digital Interface
Frequency	-
RF Type	GPS
Package / Case	56-QFN
Packaging	Tape & Reel (TR)
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	ATR0622P PYQW ATR0622PPYQW

ATR0625 General Description

The GPS baseband processor ATR0625 includes a 16-channel GPS correlator and is based on the ARM7TDMI® processor core.

This processor has a high-performance 32-bit RISC architecture and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications.

The ATR0625 has two USART and an USB device port. This port is compliant with the Universal Serial Bus (USB) V2.0 full-speed device specification. The ATR0625 includes full GPS SuperSense™ firmware, licensed from u-blox AG, which performs the basic GPS operation, including tracking, acquisition, navigation and position data output. For normal PVT (Position/Velocity/Time) applications, there is no need for off-chip Flash memory or ROM. The firmware supports the possibility to store the configuration settings in an optional external EEPROM. For customer-specific applications, a Software Development Kit is available.

The ATR0625 is manufactured using Atmel's high-density CMOS technology. By combining the ARM7TDMI microcontroller core with on-chip SRAM, 16-channel GPS correlator, and a wide range of peripheral functions on a monolithic chip, the ATR0625 provides a highly flexible and cost-effective solution for GPS applications.

ATR0625 Maximum Ratings

Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Parameters	Pin	Symbol	Min.	Max.	Unit
Operating Free Air Temperature Range			40	+85	°C
Storage Temperature			60	+150	°C
DC Supply Voltage	VDD18		0.3	+1.95	V
DC Supply Voltage	VDDIO		0.3	+3.6	V
DC Supply Voltage	VDD_USB		0.3	+3.6	V
DC Supply Voltage	LDO_IN		0.3	+3.6	V
DC Supply Voltage	LDOBAT_IN		0.3	+3.6	V
DC Supply Voltage	VBAT		0.3	+3.6	V
DC Input Voltage	P0, P15, P30, SIGHI, SIGLO, CLK23, XT_IN, TMS, TCK, TDI, NTRST, DBG_EN, LDO_EN, NRESET		0.3	+1.95	V
DC Input Voltage	USB_DM, USB_DP		0.3	+3.6	V
DC Input Voltage	P1, P2, P8, P9, P12 to P14, P16 to P27, P29, P31		0.3	+5.0	V

Note: Minimum/maximum limits are at +25°C ambient temperature, unless otherwise specified

ATR0625 Features

• 16-channel GPS Correlator
8192 Search Bins with GPS Acquisition Accelerator
Accuracy: 2.5m CEP (Stand-Alone, S/A off)
Time to First Fix: 34s (Cold Start)
Acquisition Sensitivity: 142 dBm
Tracking Sensitivity: 158 dBm
• Utilizes the ARM7TDMI® ARM^® Thumb^® Processor Core
High-performance 32-bit RISC Architecture
High-density 16-bit Instruction Set
Embedded ICE (In-circuit Emulator)
• 128 Kbyte Internal RAM
• 384 Kbyte Internal ROM with u-blox GPS Firmware
• 6-channel Peripheral Data Controller (PDC)
• 8-level Priority, Individually Maskable, Vectored Interrupt Controller
2 External Interrupts
• 24 User-programmable I/O Lines
• 1 USB Device Port
Universal Serial Bus (USB) V2.0 Full-speed Device
Embedded USB V2.0 Full-speed Transceiver
Suspend/Resume Logic
Ping-pong Mode for Isochronous and Bulk Endpoints
• 2 USARTs
2 Dedicated Peripheral Data Controller (PDC) Channels per USART
• Master/Slave SPI Interface
2 Dedicated Peripheral Data Controller (PDC) Channels
8-bit to 16-bit Programmable Data Length
4 External Slave Chip Selects
• Programmable Watchdog Timer
• Advanced Power Management Controller (APMC)
Peripherals Can Be Deactivated Individually
Geared Master Clock to Reduce Power Consumption
Sleep State with Disabled Master Clock
Hibernate State with 32.768 kHz Master Clock
• Real Time Clock (RTC)
• 2.3V to 3.6V or 1.8V Core Supply Voltage
• Includes Power Supervisor
• 1.8V to 3.3V User-definable I/O Voltage for Several GPIOs with 5V Tolerance
• 4 Kbytes Battery Backup Memory
• 8 mm * 8 mm 56 Pin QFN56 Package
• Pb-free, RoHS-compliant, Green

ATR0625 Connection Diagram

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