mPD705100

• High-performance 32-bit architecture for

• 16-bit bus fixing function incorporation use • 16-bit bus system construction
• Built-in cache memory

• Instructions suitable for variable application Instruction cache : 4K bytes • Sum-of-products operation Data cache : 4K bytes

• Saturable operation
• Built-in RAM

• Branch prediction
Instruction RAM : 4K bytes

• Concatenation shift Data RAM : 4K bytes • Block transfer instructions
• One-clock-pitch pipeline structure

• Power-saving mode
• 16-/32-bit instructions

• Maximum operating frequency
• Separate buses for addresses and data

• 100 MHz (internal)
• 4G-byte linear addresses

• 50/33 MHz (external)
• Thirty-two 32-bit general-purpose registers

• CMOS operation, 3.3-V operation
• Hardware-interlocked register/flag hazard
• 16-level interrupt responses