Features: · In-System Programmable(ISP™) Analog
- Instrument Amplifier Gain Stage
- Precision Active Filtering (10kHz to 75kHz)
- Continuous-Time Fifth Order Low Pass Topology
- Dual, A/B Configuration Memory
- Non-Volatile E2CMOS®Cells
- IEEE 1149.1 JTAG Serial Port Programming
· Unique Flexibility and Performance
- Programmable Gain Range (0dB to 20dB)
- Implements Multiple Filter Types: Elliptical, Chebyshev, Butterworth
- Low Distortion (THD < -80dB at 10kHz)
- Auto-Calibrated Input Offset Voltage
· True Differential I/O
- High CMR Instrument Amplifier Input
- 2.5V Common Mode Reference on Chip
- Rail-to-Rail Voltage Outputs
· Single Supply 5V Operation
- Power Dissipation of 133mW
- 16-Pin Plastic SOIC, PDIP Packages
· Applications Include Integrated
- Single +5V Supply Signal Conditioning
- Programmable Filters With Fully Differential I/O
- Analog Front Ends, 12-Bit Data Acq. Systems
- DSP System Front End Signal Conditioning
- High-Performance Reconstruction FiltersPinout
SpecificationsSupply Voltage VS . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +7V
Logic and Analog Input Voltage Applied. . . . . . . . . . . . . . . 0 to VS
Logic and Analog Output Short Circuit Duration . . . . . . Indefinite
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . . . .260°C
Ambient Temperature with Power Applied . . . . . . . . -55 to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C
Note: Stresses above those listed may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied.
DescriptionThe ispPAC81 is a member of the Lattice family of In-System Programmable analog circuits, digitally configured via nonvolatile E 2 CMOS technology.
Analog building blocks, called PACell™(s), replace traditional analog components such as opamps, eliminating the need for external resistors and capacitors. With no requirement for external configuration components, ispPAC81 expedites the design process, simplifying prototype circuit implementation and change, while providing high-performance integrated functionality. With all components on chip, there is no longer a concern of performance degradation due to component mismatch or other external factors. The ispPAC81 provides reliable and repeatable performance, every time.
Designers configure the ispPAC81 and verify its performance using PAC-Designer ® , an easy-to-use, Microsoft Windows ® compatible program. A filter configuration database is provided whereby thousands of different configurations can be realized. No special understanding of filter synthesis is required beyond that of general specifications such as corner frequency and stopband attenuation, etc. The software lists the possible choices that meet the designer's specifications which can then be loaded directly into either of two device (A/ B) configurations from the lookup table. Device programming is supported using PC parallel port I/O operations.
The ispPAC81 is configured through its IEEE Standard 1149.1 compliant serial port. The flexible In-System Programming capability enables programming, verification and reconfiguration, if desired, directly on the printedcircuit board.
ispPAC81 Data Sheet
