ispPAC30

Supply Voltage VS . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7V
Logic and Analog Input Voltage Applied. . . . . . . . . . . . . . .0 to V_S
Logic and Analog Output Short Circuit Duration . . . . . . Indefinite
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . . . .260
Ambient Temperature with Power Applied . . . . . . . . -55 to 125
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65 to 150
Note: Stresses above those listed may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied.

The ispPAC®30 is a member of the Lattice family of In-System Programmable (ISP™) analog integrated circuits.It is digitally configured via SRAM and utilizes E2CMOS memory for non-volatile storage of its configuration.The flexibility of ISP enables programming, verification and unlimited reconfiguration, directly on the printed circuit board.

The ispPAC30 is a complete front end solution for data acquisition applications using 10 to 12-bit ADC's. It provides multiple single-ended or differential signal inputs,multiplexing, precision gain, offset adjustment, filtering,and comparison functionality. It also has complete routability of inputs or outputs to any input cell and then from any input cell to either summing node of the two output amplifiers. Designers configure the ispPAC30 and verify its performance using PAC-Designer®, an easy to use, Microsoft Windows® compatible development tool. Device programming is supported using PC parallel port I/O operations.