Features: ` HIGH DENSITY NAND FLASH MEMORIES
Up to 8 Gbit memory array
Up to 64Mbit spare area
Cost effective solutions for mass storage applications
` NAND INTERFACE
x8 or x16 bus width
Multiplexed Address/ Data
Pinout compatibility for all densities
` SUPPLY VOLTAGE
1.8V device: VDD = 1.7 to 1.95V
3.0V device: VDD = 2.7 to 3.6V
` PAGE SIZE
x8 device: (2048 + 64 spare) Bytes
x16 device: (1024 + 32 spare) Words
` BLOCK SIZE
x8 device: (128K + 4K spare) Bytes
x16 device: (64K + 2K spare) Words
` PAGE READ / PROGRAM
Random access: 25s (max)
Sequential access: 50ns (min)
Page program time: 300s (typ)
` COPY BACK PROGRAM MODE
Fast page copy without external buffering
` CACHE PROGRAM AND CACHE READ MODES
Internal Cache Register to improve the program and read throughputs
` FAST BLOCK ERASE
Block erase time: 2ms (typ)
` STATUS REGISTER
` ELECTRONIC SIGNATURE
` CHIP ENABLE 'DON'T CARE'
for simple interface with microcontroller
` SERIAL NUMBER OPTION
` DATA PROTECTION
Hardware and Software Block Locking
Hardware Program/Erase locked during Power transitions
` DATA INTEGRITY
100,000 Program/Erase cycles
10 years Data Retention
` RoHS COMPLIANCE
Lead-Free Components are Compliant with the RoHS Directive
` DEVELOPMENT TOOLS
Error Correction Code software and hardware models
Bad Blocks Management and Wear Leveling algorithms
PC Demo board with simulation software
File System OS Native reference software
Hardware simulation modelsPinout
SpecificationsStressing the device above the ratings listed in Table 19., Absolute Maximum Ratings, may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
| Symbol |
Parameter |
Value |
Unit |
| Min |
Max |
| TBIAS |
Temperature Under Bias |
50 |
125 |
°C |
| TSTG |
Storage Temperature |
65 |
150 |
°C |
| TLEAD |
Lead temperature during soldering (2) |
|
260 |
°C |
| VIO (1) |
Input or Output Voltage |
1.8V devices |
0.6 |
2.7 |
V |
| 3 V devices |
0.6 |
4.6 |
V |
| VDD |
Supply Voltage |
1.8V devices |
0.6 |
2.7 |
V |
| 3 V devices |
0.6 |
4.6 |
V |
DescriptionThe NAND Flash 2112 Byte/ 1056 Word Page is a family of non-volatile Flash memories that uses NAND cell technology. The NAND02G-B devices range from 1 Gbit to 8 Gbits and operate with either a 1.8V or 3V voltage supply.
The size of a Page is either 2112 Bytes (2048 + 64 spare) or 1056 Words (1024 + 32 spare) depending on whether the NAND02G-B device has a x8 or x16 bus width.
The address lines of NAND02G-B are multiplexed with the Data Input/ Output signals on a multiplexed x8 or x16 Input/ Output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint.
Each block can be programmed and erased over 100,000 cycles. To extend the lifetime of NAND Flash devices it is strongly recommended to implement an Error Correction Code (ECC).
The NAND02G-B devices have hardware and software security features:
`A Write Protect pin is available to give a hardware protection against program and erase operations.
`A Block Locking scheme is available to provide user code and/or data protection.
The NAND02G-B devices feature an open-drain Ready sy output that can be used to identify if the Program/ Erase/Read (P/E/R) Controller is currently active. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor.
A Copy Back Program command is available to optimize the management of defective blocks. When a Page Program operation fails, the data can be programmed in another page without having to resend the data to be programmed. Each NAND02G-B device has Cache Program and Cache Read features which improve the program and read throughputs for large files. During Cache Programming, the device loads the data in a Cache Register while the previous data is transferred to the Page Buffer and programmed into the memory array. During Cache Reading, the device loads the data in a Cache Register while the previous data is transferred to the I/O Buffers to be read.
All NAND02G-B devices have the Chip Enable Don't Care feature, which allows code to be directly downloaded by a microcontroller, as Chip Enable transitions during the latency time do not stop the read operation. All devices have the option of a Unique Identifier (serial number), which allows each device to be uniquely identified.
The Unique Identifier options of NAND02G-B is subject to an NDA (Non Disclosure Agreement) and so not described in the datasheet. For more details of this option contact your nearest ST Sales office.
The NAND02G-B devices are available in the following packages:
`TSOP48 (12 x 20mm) for all products
`VFBGA63 (9.5 x 12 x 1mm, 0.8mm pitch) for 1Gb products
`TFBGA63 (9.5 x 12 x 1.2mm, 0.8mm pitch) for 2Gb Dual Die products
For information on how to order these options refer to Table 29., Ordering Information Scheme. NAND02G-B are shipped from the factory with Block 0 always valid and the memory content bits, in valid blocks, erased to '1'. See Table 2., Product Description, for all the devices available in the family.
NAND02G-B Data Sheet
