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NAND S

Features: · Wide supply voltage range................3V to 15V· Low power ..................................100 nW (typ.)· High noise immunity ..................0.45 VDD (typ.)· Separate SET and RESET inputs for each latch· NOR and NAND configuration·TRI-STATE output with common output enableAppli...

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SeekIC No. : 004432662 Detail

NAND S: Features: · Wide supply voltage range................3V to 15V· Low power ..................................100 nW (typ.)· High noise immunity ..................0.45 VDD (typ.)· Separate SET and RES...

NAND S Data Sheet

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Part Number:
NAND S
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/22

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Product Details

Description



Features:

· Wide supply voltage range................3V to 15V
· Low power ..................................100 nW (typ.)
· High noise immunity ..................0.45 VDD (typ.)
· Separate SET and RESET inputs for each latch
· NOR and NAND configuration
·TRI-STATE output with common output enable


Application

· Multiple bus storage
· Strobed register
· Four bits of independent storage with output enable
· General digital logic


Pinout

If Military/Aerospace specified devices are required, please contact the National Semiconductor ales Office/Distributors for availability and specifications.
Supply Voltage (VDD) ...........................- 0.5V to a18V
Input Voltage (VIN) ......................- 0.5V to VDD a0.5V
Storage Temperature Range (TS)...... - 65 to a150
Power Dissipation (PD)
Dual-In-Line................................................... 700 mW
Small Outline ..................................................500 mW
Lead Temperature (TL)
(Soldering, 10 seconds)..................................... 260
Recommended Operating
CD4043BM, CD4044BM .....................- 55to a125
CD4043BC, CD4044BC...................... - 40 to a85


Description

CD4043BM/CD4043BC are quad cross-couple TRI-STATE CMOS NOR latches, and CD4044BM/CD4044BC are quad cross-couple TRI-STATE CMOS NAND latches. Each CD4043BM/CD4043BC latch has a separate Q output and individual SET and RESET inputs. There is a common TRI-STATE ENABLE input for all four latches. A logic ``1'' on the ENABLE input connects the latch states to the Q outputs. A logic ``0'' on the ENABLE input disconnects the latch states from the Q outputs resulting in an open circuit condition on the Q output. The TRI-STATE feature allows common bussing of the outputs.




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