HM-6551

Features: •This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1.•Low Power Standby. . . . . . . . . . . . . . . . . . . . . 50W Max•Low Power Operation. . . . . . . . . . . . . . . .20mW/MHz Max•Fast Access T...

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HM-6551 Picture
SeekIC No. : 004363595 Detail

HM-6551: Features: •This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1.•Low Power Standby. . . . . . . . . . . . . . . . . . . ...

floor Price/Ceiling Price

Part Number:
HM-6551
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/25

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Product Details

Description



Features:

•This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1.
•Low Power Standby. . . . . . . . . . . . . . . . . . . . . 50W Max
•Low Power Operation. . . . . . . . . . . . . . . .20mW/MHz Max
•Fast Access Time. . . . . . . . . . . . . . . . . . . . . . . 220ns Max
•Data Retention. . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min
•TTL Compatible Input/Output
•High Output Drive - 1 TTL Load
•Internal Latched Chip Select
•High Noise Immunity
•On-Chip Address Register
•Latched Outputs
•Three-State Output



Pinout

  Connection Diagram


Specifications

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V
Input, Output or I/O Voltage. . . . . . . . . . .. . . GND -0.3V to VCC +0.3V
ESD Classification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.




Description

The HM-6551/883 is a 256 x 4 static CMOS RAM fabricated using self-aligned silicon gate technology. Synchronous circuit design techniques are employed to achieve high performance and low power operation. On chip latches are provided for address and data outputs allowing efficient interfacing with microprocessor systems. The data output buffers can be forced to a high impedance state for use in expanded memory arrays.

The HM-6551/883 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed over temperature.




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