Features: Power supply - VDD: 3.3V VDDQ : 3.3V LVTTL compatible with multiplexed address Two banks / Pulse RAS MRS cycle with address key programs- CAS Latency (2 & 3) - Burst Length (1,2,4,8 & full page) - Burst Type (Sequential & Interleave) Clock Frequency (max) : 167MHz @ CL=3 (-6)...
A43L0632: Features: Power supply - VDD: 3.3V VDDQ : 3.3V LVTTL compatible with multiplexed address Two banks / Pulse RAS MRS cycle with address key programs- CAS Latency (2 & 3) - Burst Length (1,2,4,8 &a...
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DescriptionThe A43L0616AV-7 is one member of the A43L0616 family which is designed as the 16,777,2...
Power supply
- VDD: 3.3V VDDQ : 3.3V
LVTTL compatible with multiplexed address
Two banks / Pulse RAS
MRS cycle with address key programs
- CAS Latency (2 & 3)
- Burst Length (1,2,4,8 & full page)
- Burst Type (Sequential & Interleave)
Clock Frequency (max) : 167MHz @ CL=3 (-6)
143MHz @ CL=3 (-7)
All inputs are sampled at the positive going edge of the system clock
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle) Industrial operating temperature range: -40 to +85 for -U series.
Available in 90 Balls CSP (8mm X 13mm)
Package is available to lead free (-F series)
Voltage on any pin relative to VSS (Vin, Vout ) . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +4.6V
Voltage on VDD supply relative to VSS (VDD, VDDQ )
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to + 4.6V
Storage Temperature (TSTG) . . . . . . . . . . - 55C to +150C
Soldering Temperature X Time (TSLODER) . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C X 10sec
Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . 0.8W
Short Circuit Current (Ios) . . . . . . . . . . . . . . . . . . . . 50mA
The A43L0632 is 33,554,432 bits synchronous high data rate Dynamic RAM organized as 2 X 524,288 words by 32 bits, fabricated with AMICs high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.