Features: • Supports Telcordia GR-1244-CORE Stratum 4 timing for DS1 interfaces• Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interfaces• Selectable 19.44 MHz, 2.048MHz, 1.544MHz or 8kHz input reference signals• Provides C1.5, C2, C4, C6, C8, CC16, and ...
ZL30409: Features: • Supports Telcordia GR-1244-CORE Stratum 4 timing for DS1 interfaces• Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interfaces• Selectable 19.44 MHz,...
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Parameter | Symbol | Min. | Max. | UNIT | |
1 | Supply voltage | VDD | -0.3 | 7.0 | V |
2 | Voltage on any pin | VPIN | -0.3 | VDD+ 0.3 | V |
3 | Current on any pin | IPIN | 30 | mA | |
4 | Storage temperature | TST | -55 | 125 | |
5 | 48 SSOP package power dissipation | PPD | 200 | mW |
The ZL30409 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links.
The ZL30409 generates ST-BUS clock and framing signals that are phase locked to either a 19.44 MHz, 2.048MHz, 1.544MHz, or 8kHz input reference.