ZL30117

• Synchronizes with standard telecom system references and synthesizes a wide variety of protected telecom line interface clocks that are compliant with Telcordia GR-253-CORE and ITU-T G.813
• Internal APLL provides standard output clock frequencies up to 622.08 MHz that meet jitter requirements for interfaces up to OC-192/STM-64
• Programmable output synthesizer generates clock frequencies from any multiple of 8 kHz up to 77.76 MHz in addition to 2 kHz
• Digital Phase Locked-Loop (DPLL) provides all the features necessary for generating SONET/SDH compliant clocks including automatic hitless reference switching, automatic mode selection (locked, free-run, holdover), and selectable loop bandwidth
• Provides 3 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.76 MHz in addition to 2 kHz
• Provides 3 sync inputs for output frame pulse alignment
• Generates several styles of output frame pulses with selectable pulse width, polarity, and frequency
• Configurable input to output delay, and output to output phase alignment
• Flexible input reference monitoring automatically disqualifies references based on frequency and phase irregularities
• Supports IEEE 1149.1 JTAG Boundary Scan