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ZL30111

Features: • Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 19.44 MHz input• Provides a range of clock outputs: 2.048 MHz, 4.096 MHz and 8.192 MHz• Provides 2 styles of 8 kHz framing pulses• Automatic entry and exit from freerun mode on reference fail• Provides DPLL lo...

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SeekIC No. : 004550949 Detail

ZL30111: Features: • Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 19.44 MHz input• Provides a range of clock outputs: 2.048 MHz, 4.096 MHz and 8.192 MHz• Provides 2 styles of 8 kHz framin...

ZL30111 Data Sheet

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Part Number:
ZL30111
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 19.44 MHz input
• Provides a range of clock outputs: 2.048 MHz, 4.096 MHz and 8.192 MHz
• Provides 2 styles of 8 kHz framing pulses
• Automatic entry and exit from freerun mode on reference fail
• Provides DPLL lock and reference fail indication
• DPLL bandwidth of 922 Hz for all rates of input reference and 58 Hz for an 8 kHz input reference
• Less than 0.6 nspp intrinsic jitter on all output clocks
• 20 MHz external master clock source: clock oscillator or crystal
• Simple hardware control interface


Application

• Synchronizer for POTS line cards
• Rate convert NTR 8kHz or GPON physical interface clock to TDM clock


Pinout

Connection Diagram


Specifications

 
Parameter
Symbol
Min.
Max.
Units
1 Supply voltage
VDD_R
-0.5
4.6
V
2 Core supply voltage
VCORE_R
-0.5
2.5
V
3 Voltage on any digital pin
VPIN
-0.5
6
V
4 Voltage on OSCi and OSCo pin
VOSC
-0.3
VDD + 0.3
V
5 Current on any pin
IPIN
30
mA
6 Storage temperature
TST
-55
125
7 TQFP 64 pin package power dissipation
PPD
500
mW
8 ESD rating
VESD
2
kV
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
* Voltages are with respect to ground (GND) unless otherwise stated.


Description

The ZL30111 POTS line card PLL contains a digital phase-locked loop (DPLL), which provides timing and synchronization for SLIC/CODEC devices.

The ZL30111 generates TDM clock and framing signals that are phase locked to the input reference. It helps ensure system reliability by monitoring its reference for stability and by maintaining stable output clocks during short periods when the reference is unavailable.




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