XRK697H73

The XRK697H73 is a PLL based LVCMOS Clock Generator targeted for high performance and low skew clock distribution applications. The XRK697H73 can select between one of three reference inputs and provides 14 LVCMOS outputs -12 outputs (3 banks of 4) for clock distribution, 1 for feedback and 1 for synchronization.

The XRK697H73 is a highly flexible device. It has 3 selectable inputs, (one differential and two single-ended inputs) to support system clock redundancy. Up to three different clock frequencys can be generated and outputted on the three output banks. Switching the internal reference clock is controlled by the control input, CLK_SEL.

The XRK697H73 uses PLL technology to frequency lock its outputs to the input reference clock. The divider in the feedback path will determine the frequency of the VCO. Each of the separate output banks can individually divide down the VCO output frequency. This allows the XRK697H73 to generate a multitude of different bank frequency ratios and output-to-input frequency ratios.

The outputs of the XRK697H73 can individually be immobilized, in the low state, by use of the clock stop feature. All outputs except QC0 and QFB can be immobilized through a 2 pin serial interface. Global output disabling and reset can be achieved the control input MR/OE.

The XRK697H73 also has a QSYNC output which can be used for system synchronization purposes. It monitors Bank A and Bank C outputs and goes low one period of the faster clock prior to coincident rising edges of Bank A and Bank C clocks. QSYNC then goes high again when the coincident rising edges of Bank A and Bank C occur. This feature is used primarily in applications where Bank A and Bank C are running at different frequencies, and is particularly useful when they are running at non-integer multiples of one another.

The XRK697H73 has an output frequency range of 8.33MHz to 240MHz and an input frequency range of 5MHz to 120MHz.