XRK69774

The XRK69774 is a PLL based LVCMOS Clock Generator targeted for high performance and low skew clock distribution applications. The XRK69774 can select between one of two reference inputs and provides 15 LVCMOS outputs -14 outputs (2 banks of 5 and 1 bank of 4) for clock distribution and 1 for feedback.

The XRK69774 has two LVCMOS inputs to support clock redundancy. Switching the internal reference clock is controlled by the control input, CLK_SEL.

The XRK69774 uses PLL technology to frequency lock its outputs to the input reference clock. The divider in the feedback path will determine the frequency of the VCO. Each of the separate output banks can individually divide down the VCO output frequency. This allows the XRK69774 to generate a multitude of different bank frequency ratios and output-to-input frequency ratios.

The outputs of the XRK69774 can be immobilized, in the low state, by use of the stop clock feature. Global output disabling and reset can be achieved with the control input MR/OE.

The XRK69774 has an output frequency range of 8.33MHz to125MHz and an input frequency range of 4.16MHz to 62.5MHz.