XRK69772

The XRK69772 is a PLL based LVCMOS Clock Generator targeted for high performance and low skew clock distribution applications. The XRK69772 can select between one of three reference inputs and provides 14 LVCMOS outputs -12 outputs (3 banks of 4) for clock distribution, 1 for feedback and 1 for synchronization.

The XRK69772 is a highly flexible device. It can be configured to accept either a crystal oscillator input or one of two LVCMOS compatible inputs for use as the input reference clock source. To support clock redundancy, two LVCMOS inputs are provided. Switching the internal reference clock is controlled by the control input, CLK_SEL.

The XRK69772 uses PLL technology to frequency lock its outputs to the input reference clock. The divider in the feedback path will determine the frequency of the VCO. Each of the separate output banks can individually divide down the VCO output frequency. This allows the XRK69772 to generate a multitude of different bank frequency ratios and output- to-input frequency ratios.

The outputs of the XRK69772 can individually be immobilized, in the low state, by use of the stop clock feature. All outputs except QC0 and QFB can be immobilized through a 2 pin serial interface. Global output disabling and reset can be achieved the control input MR/OE.

The XRK69772 also has a QSYNC output which can be used for system synchronization purposes. It monitors Bank A and Bank C outputs and goes low one period of the faster clock prior to coincident rising edges of Bank A and Bank C clocks. QSYNC then goes high again when the coincident rising edges of Bank A and Bank C occur. This feature is used primarily in applications where Bank A and Bank C are running at different frequencies, and is particularly useful when they are running at non-integer multiples of one another.

The XRK69772 has an output frequency range of 8.33MHz to125MHz and an input frequency range of 5MHz to 120MHz.