XRK4993

The XRK4993 is a 3.3V High-Speed Low-Voltage Programmable Skew Clock Buffer. It is intended for high-performance computer systems and offers user selectable control over system clock functions to optimize timing. Eight ouputs, arranged in four banks, can each drive 75 terminated transmission lines while delivering minimal and specified output skews and full-swing Low Voltage TTL logic levels.

Banks A, B, C (two outputs per bank) can be individually selected for one of nine delay or function configurations through two dedicated three-level inputs. These outputs are able to lead or lag the CLKIN input reference clock by up to 6 time units from their nominal "zero" skew position. The integrated PLL allows external load and transmission line delay effects to be canceled achieving zero delay capability. Combining the zero delay capability with the selectable output skew functions, output-to-output delays of up to +12 time units can be created.

The XRK4993's divide functions (divide-by-two and divide-by-four) allow distribution of a low-frequency clock that can be multiplied by two or four at the clock destination. This feature facilitates clock distribution while allowing maximum system clock flexibility.

When the OE pin is held low, all the outputs are synchronously enabled. However, if OE is held high, all the outputs except QC0 and QC1 are synchronously disabled.

When PE is held high, all the outputs are synchronized with the positive edge of the CLKIN clock input. When PE is held low, all the outputs are synchronized with the negative edge of CLKIN. The device has LVTTL outputs with 12mA balanced drive.