XRK49911

Features: • 3.75- to 110-MHz output operation• All output pair skew <100 ps typical• Three skew grades-2 : tSKEW0<250ps-5 : tSKEW0<500ps-7 : tSKEW0<700ps• Selectable output functionsSkew adjustments of +/- 6tU (up to 18 ns)Inverted and non-invertedOperation at 1...

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XRK49911 Picture
SeekIC No. : 004549378 Detail

XRK49911: Features: • 3.75- to 110-MHz output operation• All output pair skew <100 ps typical• Three skew grades-2 : tSKEW0<250ps-5 : tSKEW0<500ps-7 : tSKEW0<700ps• Selecta...

floor Price/Ceiling Price

Part Number:
XRK49911
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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268 Transactions

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Upload time: 2024/11/23

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Product Details

Description



Features:

• 3.75- to 110-MHz output operation
• All output pair skew <100 ps typical
• Three skew grades
-2 : tSKEW0<250ps
-5 : tSKEW0<500ps
-7 : tSKEW0<700ps
• Selectable output functions
Skew adjustments of +/- 6tU (up to 18 ns)
Inverted and non-inverted
Operation at 1/2 and 1/4 input frequency
Operation at 2x and 4x input frequency
• Cycle-Cycle Jitter
< 25 ps (rms)
< 200 ps (pk-pk)
• Zero input-to-output delay
• 50% duty-cycle outputs
• LVTTL outputs drive 50 terminated lines
• Operates from a single 3.3V supply
• 32-pin PLCC package
• Green packaging
• Lead free lead frame available



Pinout

  Connection Diagram


Specifications

Storage Temperature
65°C to +150°C
Ambient Temperature with Power Applied
55°C to +125°C
Supply Voltage to Ground Potential
0.5V to +7.0V
DC Input Voltage
0.5V to +7.0V
Output Current into Outputs (LOW)
64 mA
Static Discharge Voltage (per MIL-STD-883, Method 3015)
>3000V
Latch-Up Current.
>200 mA



Description

The XRK49911 is a 3.3V High-Speed Low-Voltage Programmable Skew Clock Buffer. It is intended for high-performance computer systems and offers user selectable control over system clock functions to optimize timing. Eight outputs, arranged in four banks, can each drive 50 terminated transmission lines while delivering minimal and specified output skews and full-swing Low Voltage TTL logic levels.

Each bank (two outputs per bank) can be individually selected for one of nine delay or function configurations through two dedicated tri-level inputs. These outputs are able to lead or lag the CLKIN input reference clock by up to 6 time units from their nominal "zero" skew position. The integrated PLL allows external load and transmission line delay effects to be canceled achieving zero delay capability. Combining the zero delay capability with the selectable output skew functions, output-to-output delays of up to ±12 time units can be created.

The XRK49911's divide functions (divide-by-two and divide-by-four) allow distribution of a low-frequency clock that can be multiplied by two or four at the clock destination. This feature facilitates clock distribution while allowing maximum system clock flexibility.




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